prev_cmp_ff.map.qmsg

QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 14 12:12:12 2008 " "Info: Processing started: Sun Dec 14 12:12:12 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ff -c ff " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ff -c ff" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7dec.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg7dec.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7dec-ver3 " "Info: Found design unit 1: seg7dec-ver3" {  } { { "seg7dec.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/seg7dec.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7dec " "Info: Found entity 1: seg7dec" {  } { { "seg7dec.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/seg7dec.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lifttt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lifttt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lift-lift_arch " "Info: Found design unit 1: lift-lift_arch" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 22 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lift " "Info: Found entity 1: lift" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ff.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ff.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ff " "Info: Found entity 1: ff" {  } { { "ff.bdf" "" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ff " "Info: Elaborating entity \"ff\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lift lift:inst2 " "Info: Elaborating entity \"lift\" for hierarchy \"lift:inst2\"" {  } { { "ff.bdf" "inst2" { Schematic "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/ff.bdf" { { 40 184 344 200 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "hand lifttt.vhd(26) " "Warning (10541): VHDL Signal Declaration warning at lifttt.vhd(26): used implicit default value for signal \"hand\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 26 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ur lifttt.vhd(52) " "Warning (10631): VHDL Process Statement warning at lifttt.vhd(52): inferring latch(es) for signal or variable \"ur\", which holds its previous value in one or more paths through the process" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dr lifttt.vhd(52) " "Warning (10631): VHDL Process Statement warning at lifttt.vhd(52): inferring latch(es) for signal or variable \"dr\", which holds its previous value in one or more paths through the process" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ladd lifttt.vhd(69) " "Warning (10631): VHDL Process Statement warning at lifttt.vhd(69): inferring latch(es) for signal or variable \"ladd\", which holds its previous value in one or more paths through the process" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "divide lifttt.vhd(108) " "Warning (10492): VHDL Process Statement warning at lifttt.vhd(108): signal \"divide\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 108 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ladd\[0\] lifttt.vhd(69) " "Info (10041): Inferred latch for \"ladd\[0\]\" at lifttt.vhd(69)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "ladd\[1\] lifttt.vhd(69) " "Info (10041): Inferred latch for \"ladd\[1\]\" at lifttt.vhd(69)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 69 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dr\[1\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"dr\[1\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dr\[2\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"dr\[2\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dr\[3\] lifttt.vhd(52) " "Info (10041): Inferred latch for \"dr\[3\]\" at lifttt.vhd(52)" {  } { { "lifttt.vhd" "" { Text "F:/研究生课程/可编程逻辑课件/原理课课件/期末课程设计/ff/lifttt.vhd" 52 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}