ff.map.rpt

QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。

+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |ff                        ; 106 (0)     ; 9            ; 0           ; 26   ; 97 (0)       ; 1 (0)             ; 8 (0)            ; 0 (0)           ; 0 (0)      ; |ff                 ; work         ;
;    |lift:inst2|            ; 93 (93)     ; 9            ; 0           ; 0    ; 84 (84)      ; 1 (1)             ; 8 (8)            ; 0 (0)           ; 0 (0)      ; |ff|lift:inst2      ; work         ;
;    |seg7dec:inst4|         ; 7 (7)       ; 0            ; 0           ; 0    ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ff|seg7dec:inst4   ; work         ;
;    |seg7dec:inst|          ; 6 (6)       ; 0            ; 0           ; 0    ; 6 (6)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ff|seg7dec:inst    ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                 ;
+-----------------------------------------------------+----------------------+------------------------+
; Latch Name                                          ; Latch Enable Signal  ; Free of Timing Hazards ;
+-----------------------------------------------------+----------------------+------------------------+
; lift:inst2|ladd[1]                                  ; lift:inst2|ladd[1]~5 ; yes                    ;
; lift:inst2|dr[1]                                    ; lift:inst2|dr[1]~1   ; yes                    ;
; lift:inst2|ur[1]                                    ; lift:inst2|ur[1]~1   ; yes                    ;
; lift:inst2|ur[2]                                    ; lift:inst2|ur[2]~2   ; yes                    ;
; lift:inst2|dr[2]                                    ; lift:inst2|dr[2]~0   ; yes                    ;
; lift:inst2|dr[3]                                    ; lift:inst2|dr[3]~7   ; yes                    ;
; lift:inst2|ur[3]                                    ; lift:inst2|ur[3]~3   ; yes                    ;
; lift:inst2|dr[4]                                    ; lift:inst2|dr[4]~8   ; yes                    ;
; lift:inst2|ur[4]                                    ; lift:inst2|ur[4]~4   ; yes                    ;
; lift:inst2|dr[5]                                    ; lift:inst2|dr[5]~9   ; yes                    ;
; lift:inst2|ur[5]                                    ; lift:inst2|ur[5]~5   ; yes                    ;
; lift:inst2|dr[6]                                    ; lift:inst2|dr[6]~10  ; yes                    ;
; lift:inst2|ur[6]                                    ; lift:inst2|ur[6]~6   ; yes                    ;
; lift:inst2|ladd[0]                                  ; lift:inst2|ladd[0]~0 ; yes                    ;
; Number of user-specified and inferred latches = 14  ;                      ;                        ;
+-----------------------------------------------------+----------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+-----------------------------------------------------------------------+
; Registers Removed During Synthesis                                    ;
+---------------------------------------+-------------------------------+
; Register name                         ; Reason for Removal            ;
+---------------------------------------+-------------------------------+
; lift:inst2|divide                     ; Merged with lift:inst2|dir[0] ;
; Total Number of Removed Registers = 1 ;                               ;
+---------------------------------------+-------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 9     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 3     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun Dec 14 12:17:57 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ff -c ff
Info: Found 2 design units, including 1 entities, in source file seg7dec.vhd
    Info: Found design unit 1: seg7dec-ver3
    Info: Found entity 1: seg7dec
Info: Found 2 design units, including 1 entities, in source file lifttt.vhd
    Info: Found design unit 1: lift-lift_arch
    Info: Found entity 1: lift
Info: Found 1 design units, including 1 entities, in source file ff.bdf
    Info: Found entity 1: ff
Info: Elaborating entity "ff" for the top level hierarchy
Info: Elaborating entity "lift" for hierarchy "lift:inst2"
Warning (10631): VHDL Process Statement warning at lifttt.vhd(52): inferring latch(es) for signal or variable "ur", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at lifttt.vhd(52): inferring latch(es) for signal or variable "dr", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at lifttt.vhd(69): inferring latch(es) for signal or variable "ladd", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at lifttt.vhd(108): signal "divide" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info (10041): Inferred latch for "ladd[0]" at lifttt.vhd(69)
Info (10041): Inferred latch for "ladd[1]" at lifttt.vhd(69)
Info (10041): Inferred latch for "dr[1]" at lifttt.vhd(52)
Info (10041): Inferred latch for "dr[2]" at lifttt.vhd(52)
Info (10041): Inferred latch for "dr[3]" at lifttt.vhd(52)
Info (10041): Inferred latch for "dr[4]" at lifttt.vhd(52)
Info (10041): Inferred latch for "dr[5]" at lifttt.vhd(52)
Info (10041): Inferred latch for "dr[6]" at lifttt.vhd(52)
Info (10041): Inferred latch for "ur[1]" at lifttt.vhd(52)
Info (10041): Inferred latch for "ur[2]" at lifttt.vhd(52)
Info (10041): Inferred latch for "ur[3]" at lifttt.vhd(52)
Info (10041): Inferred latch for "ur[4]" at lifttt.vhd(52)
Info (10041): Inferred latch for "ur[5]" at lifttt.vhd(52)
Info (10041): Inferred latch for "ur[6]" at lifttt.vhd(52)
Info: Elaborating entity "seg7dec" for hierarchy "seg7dec:inst4"
Warning (10492): VHDL Process Statement warning at seg7dec.vhd(17): signal "en" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Duplicate registers merged to single register
    Info: Duplicate register "lift:inst2|divide" merged to single register "lift:inst2|dir[0]"
Warning: Latch lift:inst2|ladd[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p3~0
Warning: Latch lift:inst2|dr[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~3
Warning: Latch lift:inst2|ur[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~1
Warning: Latch lift:inst2|ur[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~1
Warning: Latch lift:inst2|dr[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~3
Warning: Latch lift:inst2|dr[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~3
Warning: Latch lift:inst2|ur[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~1
Warning: Latch lift:inst2|dr[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~3
Warning: Latch lift:inst2|ur[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~1
Warning: Latch lift:inst2|dr[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~3
Warning: Latch lift:inst2|ur[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~1
Warning: Latch lift:inst2|dr[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~3
Warning: Latch lift:inst2|ur[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|p2~1
Warning: Latch lift:inst2|ladd[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal lift:inst2|liftor[2]
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "run_wait[3]" stuck at GND
Info: Implemented 132 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 19 output pins
    Info: Implemented 106 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings
    Info: Allocated 151 megabytes of memory during processing
    Info: Processing ended: Sun Dec 14 12:18:04 2008
    Info: Elapsed time: 00:00:07