clock.tan.rpt

基于VHDL的电子时钟设计

; N/A   ; None         ; 22.429 ns  ; counter10:u3|count[2] ; minutel[0] ; clk        ;
; N/A   ; None         ; 22.207 ns  ; counter10:u3|count[1] ; minutel[0] ; clk        ;
; N/A   ; None         ; 22.124 ns  ; counter10:u3|count[0] ; minutel[0] ; clk        ;
; N/A   ; None         ; 21.645 ns  ; counter10:u3|count[3] ; minutel[0] ; clk        ;
; N/A   ; None         ; 21.342 ns  ; counter10:u3|count[2] ; minutel[3] ; clk        ;
; N/A   ; None         ; 21.121 ns  ; counter10:u3|count[1] ; minutel[3] ; clk        ;
; N/A   ; None         ; 21.038 ns  ; counter10:u3|count[0] ; minutel[3] ; clk        ;
; N/A   ; None         ; 20.560 ns  ; counter10:u3|count[3] ; minutel[3] ; clk        ;
; N/A   ; None         ; 18.691 ns  ; counter6:u2|count[2]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 18.524 ns  ; counter6:u2|count[1]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 18.158 ns  ; counter6:u2|count[0]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 18.063 ns  ; counter6:u2|count[2]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 18.053 ns  ; counter6:u2|count[2]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 17.890 ns  ; counter6:u2|count[1]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 17.886 ns  ; counter6:u2|count[1]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 17.533 ns  ; counter6:u2|count[0]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 17.520 ns  ; counter6:u2|count[0]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 17.502 ns  ; counter6:u2|count[2]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 17.486 ns  ; counter6:u2|count[2]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 17.335 ns  ; counter6:u2|count[1]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 17.318 ns  ; counter6:u2|count[1]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 17.178 ns  ; counter6:u2|count[2]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 17.006 ns  ; counter6:u2|count[1]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 16.969 ns  ; counter6:u2|count[0]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 16.953 ns  ; counter6:u2|count[0]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 16.581 ns  ; counter6:u2|count[0]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 16.459 ns  ; counter6:u2|count[0]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 16.412 ns  ; counter6:u2|count[2]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 15.886 ns  ; counter6:u2|count[1]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 11.925 ns  ; counter10:u1|count[0] ; secondl[1] ; clk        ;
; N/A   ; None         ; 11.842 ns  ; counter10:u1|count[0] ; secondl[0] ; clk        ;
; N/A   ; None         ; 11.359 ns  ; counter10:u1|count[2] ; secondl[5] ; clk        ;
; N/A   ; None         ; 11.310 ns  ; counter10:u1|count[3] ; secondl[1] ; clk        ;
; N/A   ; None         ; 11.269 ns  ; counter10:u1|count[2] ; secondl[3] ; clk        ;
; N/A   ; None         ; 11.227 ns  ; counter10:u1|count[3] ; secondl[0] ; clk        ;
; N/A   ; None         ; 11.125 ns  ; counter10:u1|count[1] ; secondl[1] ; clk        ;
; N/A   ; None         ; 11.117 ns  ; counter10:u1|count[0] ; secondl[5] ; clk        ;
; N/A   ; None         ; 11.111 ns  ; counter10:u1|count[0] ; secondl[2] ; clk        ;
; N/A   ; None         ; 11.038 ns  ; counter10:u1|count[1] ; secondl[0] ; clk        ;
; N/A   ; None         ; 11.025 ns  ; counter10:u1|count[0] ; secondl[3] ; clk        ;
; N/A   ; None         ; 10.977 ns  ; counter10:u1|count[3] ; secondl[5] ; clk        ;
; N/A   ; None         ; 10.886 ns  ; counter10:u1|count[3] ; secondl[3] ; clk        ;
; N/A   ; None         ; 10.840 ns  ; counter10:u1|count[2] ; secondl[1] ; clk        ;
; N/A   ; None         ; 10.809 ns  ; counter10:u1|count[2] ; secondl[4] ; clk        ;
; N/A   ; None         ; 10.784 ns  ; counter10:u1|count[2] ; secondl[6] ; clk        ;
; N/A   ; None         ; 10.757 ns  ; counter10:u1|count[2] ; secondl[0] ; clk        ;
; N/A   ; None         ; 10.668 ns  ; counter10:u1|count[1] ; secondl[5] ; clk        ;
; N/A   ; None         ; 10.569 ns  ; counter10:u1|count[1] ; secondl[3] ; clk        ;
; N/A   ; None         ; 10.566 ns  ; counter10:u1|count[0] ; secondl[4] ; clk        ;
; N/A   ; None         ; 10.552 ns  ; counter10:u1|count[0] ; secondl[6] ; clk        ;
; N/A   ; None         ; 10.493 ns  ; counter10:u1|count[3] ; secondl[2] ; clk        ;
; N/A   ; None         ; 10.427 ns  ; counter10:u1|count[3] ; secondl[4] ; clk        ;
; N/A   ; None         ; 10.401 ns  ; counter10:u1|count[3] ; secondl[6] ; clk        ;
; N/A   ; None         ; 10.319 ns  ; counter10:u1|count[1] ; secondl[2] ; clk        ;
; N/A   ; None         ; 10.121 ns  ; counter10:u1|count[1] ; secondl[6] ; clk        ;
; N/A   ; None         ; 10.114 ns  ; counter10:u1|count[1] ; secondl[4] ; clk        ;
; N/A   ; None         ; 10.023 ns  ; counter10:u1|count[2] ; secondl[2] ; clk        ;
+-------+--------------+------------+-----------------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Nov 19 22:38:14 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "counter6:u4|c" as buffer
    Info: Detected ripple clock "counter10:u3|c" as buffer
    Info: Detected ripple clock "counter6:u2|c" as buffer
    Info: Detected ripple clock "counter10:u1|c" as buffer
Info: Clock "clk" has Internal fmax of 185.74 MHz between source register "counter24:u5|count[2]" and destination register "counter24:u5|count[5]" (period= 5.384 ns)
    Info: + Longest register to register delay is 4.675 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N9; Fanout = 11; REG Node = 'counter24:u5|count[2]'
        Info: 2: + IC(1.545 ns) + CELL(0.914 ns) = 2.459 ns; Loc. = LC_X2_Y7_N8; Fanout = 2; COMB Node = 'counter24:u5|Equal0~36'
        Info: 3: + IC(1.155 ns) + CELL(1.061 ns) = 4.675 ns; Loc. = LC_X1_Y7_N1; Fanout = 5; REG Node = 'counter24:u5|count[5]'
        Info: Total cell delay = 1.975 ns ( 42.25 % )
        Info: Total interconnect delay = 2.700 ns ( 57.75 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 25.394 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y8_N5; Fanout = 4; REG Node = 'counter10:u1|c'
            Info: 3: + IC(5.052 ns) + CELL(1.294 ns) = 10.541 ns; Loc. = LC_X8_Y8_N5; Fanout = 5; REG Node = 'counter6:u2|c'
            Info: 4: + IC(4.583 ns) + CELL(1.294 ns) = 16.418 ns; Loc. = LC_X10_Y10_N7; Fanout = 4; REG Node = 'counter10:u3|c'
            Info: 5: + IC(2.029 ns) + CELL(1.294 ns) = 19.741 ns; Loc. = LC_X11_Y8_N5; Fanout = 6; REG Node = 'counter6:u4|c'
            Info: 6: + IC(4.735 ns) + CELL(0.918 ns) = 25.394 ns; Loc. = LC_X1_Y7_N1; Fanout = 5; REG Node = 'counter24:u5|count[5]'
            Info: Total cell delay = 7.257 ns ( 28.58 % )
            Info: Total interconnect delay = 18.137 ns ( 71.42 % )
        Info: - Longest clock path from clock "clk" to source register is 25.394 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y8_N5; Fanout = 4; REG Node = 'counter10:u1|c'
            Info: 3: + IC(5.052 ns) + CELL(1.294 ns) = 10.541 ns; Loc. = LC_X8_Y8_N5; Fanout = 5; REG Node = 'counter6:u2|c'
            Info: 4: + IC(4.583 ns) + CELL(1.294 ns) = 16.418 ns; Loc. = LC_X10_Y10_N7; Fanout = 4; REG Node = 'counter10:u3|c'
            Info: 5: + IC(2.029 ns) + CELL(1.294 ns) = 19.741 ns; Loc. = LC_X11_Y8_N5; Fanout = 6; REG Node = 'counter6:u4|c'
            Info: 6: + IC(4.735 ns) + CELL(0.918 ns) = 25.394 ns; Loc. = LC_X1_Y7_N9; Fanout = 11; REG Node = 'counter24:u5|count[2]'
            Info: Total cell delay = 7.257 ns ( 28.58 % )
            Info: Total interconnect delay = 18.137 ns ( 71.42 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "hourh[5]" through register "counter24:u5|count[2]" is 32.670 ns
    Info: + Longest clock path from clock "clk" to source register is 25.394 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y8_N5; Fanout = 4; REG Node = 'counter10:u1|c'
        Info: 3: + IC(5.052 ns) + CELL(1.294 ns) = 10.541 ns; Loc. = LC_X8_Y8_N5; Fanout = 5; REG Node = 'counter6:u2|c'
        Info: 4: + IC(4.583 ns) + CELL(1.294 ns) = 16.418 ns; Loc. = LC_X10_Y10_N7; Fanout = 4; REG Node = 'counter10:u3|c'
        Info: 5: + IC(2.029 ns) + CELL(1.294 ns) = 19.741 ns; Loc. = LC_X11_Y8_N5; Fanout = 6; REG Node = 'counter6:u4|c'
        Info: 6: + IC(4.735 ns) + CELL(0.918 ns) = 25.394 ns; Loc. = LC_X1_Y7_N9; Fanout = 11; REG Node = 'counter24:u5|count[2]'
        Info: Total cell delay = 7.257 ns ( 28.58 % )
        Info: Total interconnect delay = 18.137 ns ( 71.42 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 6.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N9; Fanout = 11; REG Node = 'counter24:u5|count[2]'
        Info: 2: + IC(1.561 ns) + CELL(0.914 ns) = 2.475 ns; Loc. = LC_X2_Y7_N1; Fanout = 1; COMB Node = 'decoder:u10|Mux1~21'
        Info: 3: + IC(2.103 ns) + CELL(2.322 ns) = 6.900 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'hourh[5]'
        Info: Total cell delay = 3.236 ns ( 46.90 % )
        Info: Total interconnect delay = 3.664 ns ( 53.10 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 124 megabytes
    Info: Processing ended: Wed Nov 19 22:38:17 2008
    Info: Elapsed time: 00:00:03
    Info: Total CPU time (on all processors): 00:00:02