mul16.cbx.xml

基于CPLD/FPGA的十六位乘法器的VHDL实现

<?xml version="1.0" ?>
<LOG_ROOT>
	<PROJECT NAME="mul16">
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add11" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add2" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add6" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add12" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add3" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add7" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add0" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add13" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add4" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add8" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add1" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add10" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add14" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add5" CBX_FILE_NAME="add_sub_fjh.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|mul16|lpm_add_sub:Add9" CBX_FILE_NAME="add_sub_fjh.tdf"/>
	</PROJECT>
</LOG_ROOT>