prev_cmp_mul16.tan.qmsg

基于CPLD/FPGA的十六位乘法器的VHDL实现

{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "q\[8\]~reg0 b\[5\] clk 4.667 ns register " "Info: tsu for register \"q\[8\]~reg0\" (data pin = \"b\[5\]\", clock pin = \"clk\") is 4.667 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.153 ns + Longest pin register " "Info: + Longest pin to register delay is 8.153 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns b\[5\] 1 PIN PIN_86 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_86; Fanout = 3; PIN Node = 'b\[5\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[5] } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.126 ns) + CELL(0.747 ns) 6.005 ns q\[5\]~91 2 COMB LC_X4_Y7_N7 2 " "Info: 2: + IC(4.126 ns) + CELL(0.747 ns) = 6.005 ns; Loc. = LC_X4_Y7_N7; Fanout = 2; COMB Node = 'q\[5\]~91'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.873 ns" { b[5] q[5]~91 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 6.128 ns q\[6\]~93 3 COMB LC_X4_Y7_N8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 6.128 ns; Loc. = LC_X4_Y7_N8; Fanout = 2; COMB Node = 'q\[6\]~93'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { q[5]~91 q[6]~93 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 6.527 ns q\[7\]~95 4 COMB LC_X4_Y7_N9 6 " "Info: 4: + IC(0.000 ns) + CELL(0.399 ns) = 6.527 ns; Loc. = LC_X4_Y7_N9; Fanout = 6; COMB Node = 'q\[7\]~95'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.399 ns" { q[6]~93 q[7]~95 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.626 ns) 8.153 ns q\[8\]~reg0 5 REG LC_X5_Y7_N0 1 " "Info: 5: + IC(0.000 ns) + CELL(1.626 ns) = 8.153 ns; Loc. = LC_X5_Y7_N0; Fanout = 1; REG Node = 'q\[8\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.626 ns" { q[7]~95 q[8]~reg0 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.027 ns ( 49.39 % ) " "Info: Total cell delay = 4.027 ns ( 49.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.126 ns ( 50.61 % ) " "Info: Total interconnect delay = 4.126 ns ( 50.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.153 ns" { b[5] q[5]~91 q[6]~93 q[7]~95 q[8]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "8.153 ns" { b[5] {} b[5]~combout {} q[5]~91 {} q[6]~93 {} q[7]~95 {} q[8]~reg0 {} } { 0.000ns 0.000ns 4.126ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.132ns 0.747ns 0.123ns 0.399ns 1.626ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns q\[8\]~reg0 2 REG LC_X5_Y7_N0 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y7_N0; Fanout = 1; REG Node = 'q\[8\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk q[8]~reg0 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk q[8]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} q[8]~reg0 {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "8.153 ns" { b[5] q[5]~91 q[6]~93 q[7]~95 q[8]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "8.153 ns" { b[5] {} b[5]~combout {} q[5]~91 {} q[6]~93 {} q[7]~95 {} q[8]~reg0 {} } { 0.000ns 0.000ns 4.126ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.132ns 0.747ns 0.123ns 0.399ns 1.626ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk q[8]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} q[8]~reg0 {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[1\] q\[1\]~reg0 10.063 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[1\]\" through register \"q\[1\]~reg0\" is 10.063 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns q\[1\]~reg0 2 REG LC_X4_Y7_N3 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y7_N3; Fanout = 1; REG Node = 'q\[1\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk q[1]~reg0 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk q[1]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} q[1]~reg0 {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.868 ns + Longest register pin " "Info: + Longest register to pin delay is 5.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[1\]~reg0 1 REG LC_X4_Y7_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y7_N3; Fanout = 1; REG Node = 'q\[1\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { q[1]~reg0 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.546 ns) + CELL(2.322 ns) 5.868 ns q\[1\] 2 PIN PIN_101 0 " "Info: 2: + IC(3.546 ns) + CELL(2.322 ns) = 5.868 ns; Loc. = PIN_101; Fanout = 0; PIN Node = 'q\[1\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.868 ns" { q[1]~reg0 q[1] } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 39.57 % ) " "Info: Total cell delay = 2.322 ns ( 39.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.546 ns ( 60.43 % ) " "Info: Total interconnect delay = 3.546 ns ( 60.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.868 ns" { q[1]~reg0 q[1] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.868 ns" { q[1]~reg0 {} q[1] {} } { 0.000ns 3.546ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk q[1]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} q[1]~reg0 {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.868 ns" { q[1]~reg0 q[1] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.868 ns" { q[1]~reg0 {} q[1] {} } { 0.000ns 3.546ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "q\[9\]~reg0 a\[9\] clk -1.088 ns register " "Info: th for register \"q\[9\]~reg0\" (data pin = \"a\[9\]\", clock pin = \"clk\") is -1.088 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns q\[9\]~reg0 2 REG LC_X5_Y7_N1 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y7_N1; Fanout = 1; REG Node = 'q\[9\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk q[9]~reg0 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk q[9]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} q[9]~reg0 {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.128 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[9\] 1 PIN PIN_44 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_44; Fanout = 3; PIN Node = 'a\[9\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[9] } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.813 ns) + CELL(1.183 ns) 5.128 ns q\[9\]~reg0 2 REG LC_X5_Y7_N1 1 " "Info: 2: + IC(2.813 ns) + CELL(1.183 ns) = 5.128 ns; Loc. = LC_X5_Y7_N1; Fanout = 1; REG Node = 'q\[9\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.996 ns" { a[9] q[9]~reg0 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.315 ns ( 45.14 % ) " "Info: Total cell delay = 2.315 ns ( 45.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.813 ns ( 54.86 % ) " "Info: Total interconnect delay = 2.813 ns ( 54.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.128 ns" { a[9] q[9]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.128 ns" { a[9] {} a[9]~combout {} q[9]~reg0 {} } { 0.000ns 0.000ns 2.813ns } { 0.000ns 1.132ns 1.183ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk q[9]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} q[9]~reg0 {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.128 ns" { a[9] q[9]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.128 ns" { a[9] {} a[9]~combout {} q[9]~reg0 {} } { 0.000ns 0.000ns 2.813ns } { 0.000ns 1.132ns 1.183ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "122 " "Info: Peak virtual memory: 122 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 14 20:25:30 2008 " "Info: Processing ended: Fri Nov 14 20:25:30 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}