mul16.tmw_info

来自「基于CPLD/FPGA的十六位乘法器的VHDL实现」· TMW_INFO 代码 · 共 8 行

start_full_compilation:s:00:00:25
start_analysis_synthesis:s:00:00:07
start_fitter:s:00:00:08
start_assembler:s:00:00:04
start_timing_analyzer:s:00:00:06
start_quartus_simulator:s:00:00:05
start_generate_netlist:s:00:00:07