📄 mul16.tan.qmsg

📁 基于CPLD/FPGA的十六位乘法器的VHDL实现
💻 QMSG
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{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 7 -1 0 } } { "d:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "q\[28\]~reg0 b\[1\] clk 70.773 ns register " "Info: tsu for register \"q\[28\]~reg0\" (data pin = \"b\[1\]\", clock pin = \"clk\") is 70.773 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "74.259 ns + Longest pin register " "Info: + Longest pin to register delay is 74.259 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns b\[1\] 1 PIN PIN_60 18 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_60; Fanout = 18; PIN Node = 'b\[1\]'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[1] } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.067 ns) + CELL(0.511 ns) 4.710 ns temp~2824 2 COMB LC_X9_Y9_N0 3 " "Info: 2: + IC(3.067 ns) + CELL(0.511 ns) = 4.710 ns; Loc. = LC_X9_Y9_N0; Fanout = 3; COMB Node = 'temp~2824'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.578 ns" { b[1] temp~2824 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.032 ns) + CELL(0.978 ns) 8.720 ns Add0~253 3 COMB LC_X9_Y9_N2 2 " "Info: 3: + IC(3.032 ns) + CELL(0.978 ns) = 8.720 ns; Loc. = LC_X9_Y9_N2; Fanout = 2; COMB Node = 'Add0~253'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.010 ns" { temp~2824 Add0~253 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 9.535 ns Add0~254 4 COMB LC_X9_Y9_N3 3 " "Info: 4: + IC(0.000 ns) + CELL(0.815 ns) = 9.535 ns; Loc. = LC_X9_Y9_N3; Fanout = 3; COMB Node = 'Add0~254'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { Add0~253 Add0~254 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.389 ns) + CELL(0.978 ns) 12.902 ns Add1~253 5 COMB LC_X10_Y10_N2 2 " "Info: 5: + IC(2.389 ns) + CELL(0.978 ns) = 12.902 ns; Loc. = LC_X10_Y10_N2; Fanout = 2; COMB Node = 'Add1~253'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.367 ns" { Add0~254 Add1~253 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 13.025 ns Add1~255 6 COMB LC_X10_Y10_N3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.123 ns) = 13.025 ns; Loc. = LC_X10_Y10_N3; Fanout = 2; COMB Node = 'Add1~255'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add1~253 Add1~255 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 13.840 ns Add1~256 7 COMB LC_X10_Y10_N4 3 " "Info: 7: + IC(0.000 ns) + CELL(0.815 ns) = 13.840 ns; Loc. = LC_X10_Y10_N4; Fanout = 3; COMB Node = 'Add1~256'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { Add1~255 Add1~256 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.888 ns) + CELL(0.978 ns) 16.706 ns Add2~255 8 COMB LC_X12_Y10_N3 2 " "Info: 8: + IC(1.888 ns) + CELL(0.978 ns) = 16.706 ns; Loc. = LC_X12_Y10_N3; Fanout = 2; COMB Node = 'Add2~255'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.866 ns" { Add1~256 Add2~255 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 17.521 ns Add2~256 9 COMB LC_X12_Y10_N4 3 " "Info: 9: + IC(0.000 ns) + CELL(0.815 ns) = 17.521 ns; Loc. = LC_X12_Y10_N4; Fanout = 3; COMB Node = 'Add2~256'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { Add2~255 Add2~256 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.059 ns) + CELL(0.978 ns) 21.558 ns Add3~255 10 COMB LC_X12_Y8_N3 2 " "Info: 10: + IC(3.059 ns) + CELL(0.978 ns) = 21.558 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; COMB Node = 'Add3~255'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.037 ns" { Add2~256 Add3~255 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 22.373 ns Add3~256 11 COMB LC_X12_Y8_N4 3 " "Info: 11: + IC(0.000 ns) + CELL(0.815 ns) = 22.373 ns; Loc. = LC_X12_Y8_N4; Fanout = 3; COMB Node = 'Add3~256'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { Add3~255 Add3~256 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.696 ns) + CELL(0.978 ns) 26.047 ns Add4~255 12 COMB LC_X12_Y7_N3 2 " "Info: 12: + IC(2.696 ns) + CELL(0.978 ns) = 26.047 ns; Loc. = LC_X12_Y7_N3; Fanout = 2; COMB Node = 'Add4~255'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.674 ns" { Add3~256 Add4~255 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 26.862 ns Add4~256 13 COMB LC_X12_Y7_N4 3 " "Info: 13: + IC(0.000 ns) + CELL(0.815 ns) = 26.862 ns; Loc. = LC_X12_Y7_N4; Fanout = 3; COMB Node = 'Add4~256'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { Add4~255 Add4~256 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.078 ns) + CELL(0.978 ns) 30.918 ns Add5~255 14 COMB LC_X12_Y5_N3 2 " "Info: 14: + IC(3.078 ns) + CELL(0.978 ns) = 30.918 ns; Loc. = LC_X12_Y5_N3; Fanout = 2; COMB Node = 'Add5~255'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.056 ns" { Add4~256 Add5~255 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 31.179 ns Add5~257 15 COMB LC_X12_Y5_N4 6 " "Info: 15: + IC(0.000 ns) + CELL(0.261 ns) = 31.179 ns; Loc. = LC_X12_Y5_N4; Fanout = 6; COMB Node = 'Add5~257'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { Add5~255 Add5~257 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.349 ns) 31.528 ns Add5~267 16 COMB LC_X12_Y5_N9 6 " "Info: 16: + IC(0.000 ns) + CELL(0.349 ns) = 31.528 ns; Loc. = LC_X12_Y5_N9; Fanout = 6; COMB Node = 'Add5~267'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.349 ns" { Add5~257 Add5~267 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 32.762 ns Add5~268 17 COMB LC_X13_Y5_N0 2 " "Info: 17: + IC(0.000 ns) + CELL(1.234 ns) = 32.762 ns; Loc. = LC_X13_Y5_N0; Fanout = 2; COMB Node = 'Add5~268'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { Add5~267 Add5~268 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.471 ns) + CELL(1.099 ns) 36.332 ns Add6~267 18 COMB LC_X8_Y5_N9 6 " "Info: 18: + IC(2.471 ns) + CELL(1.099 ns) = 36.332 ns; Loc. = LC_X8_Y5_N9; Fanout = 6; COMB Node = 'Add6~267'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.570 ns" { Add5~268 Add6~267 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 37.566 ns Add6~268 19 COMB LC_X9_Y5_N0 2 " "Info: 19: + IC(0.000 ns) + CELL(1.234 ns) = 37.566 ns; Loc. = LC_X9_Y5_N0; Fanout = 2; COMB Node = 'Add6~268'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { Add6~267 Add6~268 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.529 ns) + CELL(1.099 ns) 41.194 ns Add7~267 20 COMB LC_X7_Y6_N9 6 " "Info: 20: + IC(2.529 ns) + CELL(1.099 ns) = 41.194 ns; Loc. = LC_X7_Y6_N9; Fanout = 6; COMB Node = 'Add7~267'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.628 ns" { Add6~268 Add7~267 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 42.428 ns Add7~268 21 COMB LC_X8_Y6_N0 2 " "Info: 21: + IC(0.000 ns) + CELL(1.234 ns) = 42.428 ns; Loc. = LC_X8_Y6_N0; Fanout = 2; COMB Node = 'Add7~268'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { Add7~267 Add7~268 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.476 ns) + CELL(1.099 ns) 46.003 ns Add8~267 22 COMB LC_X7_Y7_N9 6 " "Info: 22: + IC(2.476 ns) + CELL(1.099 ns) = 46.003 ns; Loc. = LC_X7_Y7_N9; Fanout = 6; COMB Node = 'Add8~267'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.575 ns" { Add7~268 Add8~267 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 47.237 ns Add8~268 23 COMB LC_X8_Y7_N0 2 " "Info: 23: + IC(0.000 ns) + CELL(1.234 ns) = 47.237 ns; Loc. = LC_X8_Y7_N0; Fanout = 2; COMB Node = 'Add8~268'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { Add8~267 Add8~268 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.837 ns) + CELL(1.244 ns) 50.318 ns Add9~267 24 COMB LC_X7_Y10_N9 6 " "Info: 24: + IC(1.837 ns) + CELL(1.244 ns) = 50.318 ns; Loc. = LC_X7_Y10_N9; Fanout = 6; COMB Node = 'Add9~267'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.081 ns" { Add8~268 Add9~267 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 51.552 ns Add9~268 25 COMB LC_X8_Y10_N0 2 " "Info: 25: + IC(0.000 ns) + CELL(1.234 ns) = 51.552 ns; Loc. = LC_X8_Y10_N0; Fanout = 2; COMB Node = 'Add9~268'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { Add9~267 Add9~268 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.901 ns) + CELL(1.099 ns) 54.552 ns Add10~267 26 COMB LC_X5_Y10_N9 6 " "Info: 26: + IC(1.901 ns) + CELL(1.099 ns) = 54.552 ns; Loc. = LC_X5_Y10_N9; Fanout = 6; COMB Node = 'Add10~267'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { Add9~268 Add10~267 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 55.786 ns Add10~268 27 COMB LC_X6_Y10_N0 2 " "Info: 27: + IC(0.000 ns) + CELL(1.234 ns) = 55.786 ns; Loc. = LC_X6_Y10_N0; Fanout = 2; COMB Node = 'Add10~268'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { Add10~267 Add10~268 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.897 ns) + CELL(1.099 ns) 58.782 ns Add11~267 28 COMB LC_X3_Y10_N9 6 " "Info: 28: + IC(1.897 ns) + CELL(1.099 ns) = 58.782 ns; Loc. = LC_X3_Y10_N9; Fanout = 6; COMB Node = 'Add11~267'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.996 ns" { Add10~268 Add11~267 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 60.016 ns Add11~268 29 COMB LC_X4_Y10_N0 2 " "Info: 29: + IC(0.000 ns) + CELL(1.234 ns) = 60.016 ns; Loc. = LC_X4_Y10_N0; Fanout = 2; COMB Node = 'Add11~268'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { Add11~267 Add11~268 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.962 ns) + CELL(1.244 ns) 63.222 ns Add12~267 30 COMB LC_X3_Y9_N9 6 " "Info: 30: + IC(1.962 ns) + CELL(1.244 ns) = 63.222 ns; Loc. = LC_X3_Y9_N9; Fanout = 6; COMB Node = 'Add12~267'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.206 ns" { Add11~268 Add12~267 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 64.456 ns Add12~274 31 COMB LC_X4_Y9_N3 3 " "Info: 31: + IC(0.000 ns) + CELL(1.234 ns) = 64.456 ns; Loc. = LC_X4_Y9_N3; Fanout = 3; COMB Node = 'Add12~274'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { Add12~267 Add12~274 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.524 ns) + CELL(0.978 ns) 67.958 ns Add13~273 32 COMB LC_X5_Y8_N2 2 " "Info: 32: + IC(2.524 ns) + CELL(0.978 ns) = 67.958 ns; Loc. = LC_X5_Y8_N2; Fanout = 2; COMB Node = 'Add13~273'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.502 ns" { Add12~274 Add13~273 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 68.081 ns Add13~275 33 COMB LC_X5_Y8_N3 2 " "Info: 33: + IC(0.000 ns) + CELL(0.123 ns) = 68.081 ns; Loc. = LC_X5_Y8_N3; Fanout = 2; COMB Node = 'Add13~275'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add13~273 Add13~275 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 68.896 ns Add13~276 34 COMB LC_X5_Y8_N4 3 " "Info: 34: + IC(0.000 ns) + CELL(0.815 ns) = 68.896 ns; Loc. = LC_X5_Y8_N4; Fanout = 3; COMB Node = 'Add13~276'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.815 ns" { Add13~275 Add13~276 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.988 ns) + CELL(0.747 ns) 72.631 ns q\[26\]~138 35 COMB LC_X5_Y7_N3 2 " "Info: 35: + IC(2.988 ns) + CELL(0.747 ns) = 72.631 ns; Loc. = LC_X5_Y7_N3; Fanout = 2; COMB Node = 'q\[26\]~138'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.735 ns" { Add13~276 q[26]~138 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 72.892 ns q\[27\]~140 36 COMB LC_X5_Y7_N4 4 " "Info: 36: + IC(0.000 ns) + CELL(0.261 ns) = 72.892 ns; Loc. = LC_X5_Y7_N4; Fanout = 4; COMB Node = 'q\[27\]~140'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { q[26]~138 q[27]~140 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.367 ns) 74.259 ns q\[28\]~reg0 37 REG LC_X5_Y7_N5 1 " "Info: 37: + IC(0.000 ns) + CELL(1.367 ns) = 74.259 ns; Loc. = LC_X5_Y7_N5; Fanout = 1; REG Node = 'q\[28\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.367 ns" { q[27]~140 q[28]~reg0 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "34.465 ns ( 46.41 % ) " "Info: Total cell delay = 34.465 ns ( 46.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "39.794 ns ( 53.59 % ) " "Info: Total interconnect delay = 39.794 ns ( 53.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "74.259 ns" { b[1] temp~2824 Add0~253 Add0~254 Add1~253 Add1~255 Add1~256 Add2~255 Add2~256 Add3~255 Add3~256 Add4~255 Add4~256 Add5~255 Add5~257 Add5~267 Add5~268 Add6~267 Add6~268 Add7~267 Add7~268 Add8~267 Add8~268 Add9~267 Add9~268 Add10~267 Add10~268 Add11~267 Add11~268 Add12~267 Add12~274 Add13~273 Add13~275 Add13~276 q[26]~138 q[27]~140 q[28]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "74.259 ns" { b[1] {} b[1]~combout {} temp~2824 {} Add0~253 {} Add0~254 {} Add1~253 {} Add1~255 {} Add1~256 {} Add2~255 {} Add2~256 {} Add3~255 {} Add3~256 {} Add4~255 {} Add4~256 {} Add5~255 {} Add5~257 {} Add5~267 {} Add5~268 {} Add6~267 {} Add6~268 {} Add7~267 {} Add7~268 {} Add8~267 {} Add8~268 {} Add9~267 {} Add9~268 {} Add10~267 {} Add10~268 {} Add11~267 {} Add11~268 {} Add12~267 {} Add12~274 {} Add13~273 {} Add13~275 {} Add13~276 {} q[26]~138 {} q[27]~140 {} q[28]~reg0 {} } { 0.000ns 0.000ns 3.067ns 3.032ns 0.000ns 2.389ns 0.000ns 0.000ns 1.888ns 0.000ns 3.059ns 0.000ns 2.696ns 0.000ns 3.078ns 0.000ns 0.000ns 0.000ns 2.471ns 0.000ns 2.529ns 0.000ns 2.476ns 0.000ns 1.837ns 0.000ns 1.901ns 0.000ns 1.897ns 0.000ns 1.962ns 0.000ns 2.524ns 0.000ns 0.000ns 2.988ns 0.000ns 0.000ns } { 0.000ns 1.132ns 0.511ns 0.978ns 0.815ns 0.978ns 0.123ns 0.815ns 0.978ns 0.815ns 0.978ns 0.815ns 0.978ns 0.815ns 0.978ns 0.261ns 0.349ns 1.234ns 1.099ns 1.234ns 1.099ns 1.234ns 1.099ns 1.234ns 1.244ns 1.234ns 1.099ns 1.234ns 1.099ns 1.234ns 1.244ns 1.234ns 0.978ns 0.123ns 0.815ns 0.747ns 0.261ns 1.367ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 20 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 32 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 32; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns q\[28\]~reg0 2 REG LC_X5_Y7_N5 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y7_N5; Fanout = 1; REG Node = 'q\[28\]~reg0'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk q[28]~reg0 } "NODE_NAME" } } { "mul16.vhd" "" { Text "E:/CPLD/乘法器/mul16.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk q[28]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} q[28]~reg0 {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "74.259 ns" { b[1] temp~2824 Add0~253 Add0~254 Add1~253 Add1~255 Add1~256 Add2~255 Add2~256 Add3~255 Add3~256 Add4~255 Add4~256 Add5~255 Add5~257 Add5~267 Add5~268 Add6~267 Add6~268 Add7~267 Add7~268 Add8~267 Add8~268 Add9~267 Add9~268 Add10~267 Add10~268 Add11~267 Add11~268 Add12~267 Add12~274 Add13~273 Add13~275 Add13~276 q[26]~138 q[27]~140 q[28]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "74.259 ns" { b[1] {} b[1]~combout {} temp~2824 {} Add0~253 {} Add0~254 {} Add1~253 {} Add1~255 {} Add1~256 {} Add2~255 {} Add2~256 {} Add3~255 {} Add3~256 {} Add4~255 {} Add4~256 {} Add5~255 {} Add5~257 {} Add5~267 {} Add5~268 {} Add6~267 {} Add6~268 {} Add7~267 {} Add7~268 {} Add8~267 {} Add8~268 {} Add9~267 {} Add9~268 {} Add10~267 {} Add10~268 {} Add11~267 {} Add11~268 {} Add12~267 {} Add12~274 {} Add13~273 {} Add13~275 {} Add13~276 {} q[26]~138 {} q[27]~140 {} q[28]~reg0 {} } { 0.000ns 0.000ns 3.067ns 3.032ns 0.000ns 2.389ns 0.000ns 0.000ns 1.888ns 0.000ns 3.059ns 0.000ns 2.696ns 0.000ns 3.078ns 0.000ns 0.000ns 0.000ns 2.471ns 0.000ns 2.529ns 0.000ns 2.476ns 0.000ns 1.837ns 0.000ns 1.901ns 0.000ns 1.897ns 0.000ns 1.962ns 0.000ns 2.524ns 0.000ns 0.000ns 2.988ns 0.000ns 0.000ns } { 0.000ns 1.132ns 0.511ns 0.978ns 0.815ns 0.978ns 0.123ns 0.815ns 0.978ns 0.815ns 0.978ns 0.815ns 0.978ns 0.815ns 0.978ns 0.261ns 0.349ns 1.234ns 1.099ns 1.234ns 1.099ns 1.234ns 1.099ns 1.234ns 1.244ns 1.234ns 1.099ns 1.234ns 1.099ns 1.234ns 1.244ns 1.234ns 0.978ns 0.123ns 0.815ns 0.747ns 0.261ns 1.367ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk q[28]~reg0 } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk {} clk~combout {} q[28]~reg0 {} } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
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