kzq.vhd

eda微波炉程序控制器 初学vhdl语言的控制程序设计

--KZQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY KZQ IS
 PORT(RESET,SET_T,START,TEST,CLK,DONE: IN STD_LOGIC;
COOK,LD_8888,LD_CLK,LD_DONE:OUT STD_LOGIC);
END ENTITY KZQ;
ARCHITECTURE ART OF KZQ IS
TYPE STATE_TYPE IS(IDLE,LAMP_TEST,SET_CLOCK,TIMER,DONE_MSG);
SIGNAL NXT_STATE,CURR_STATE:STATE_TYPE;
 BEGIN
	PROCESS(CLK,RESET) IS
	BEGIN
	IF RESET='1' THEN
	CURR_STATE<=IDLE;
ELSIF CLK'EVENT AND CLK='1' THEN
	 CURR_STATE<=NXT_STATE;
	END IF;
END PROCESS;
PROCESS(CLK,CURR_STATE,SET_T,START,TEST,DONE) IS
 BEGIN
	 NXT_STATE<=IDLE;  --DEFAULT NEXT STATE IS IDLE;
	LD_8888<='0';
	  LD_DONE<='0';
	LD_CLK<='0';
	COOK<='0';
	CASE CURR_STATE IS
	WHEN LAMP_TEST=> LD_8888<='1';  COOK<='0';
	WHEN SET_CLOCK=> LD_CLK<='1';  COOK<='0';
	WHEN DONE_MSG => LD_DONE<='1';  COOK<='0';
	WHEN IDLE=>
        IF(TEST='1') THEN
          NXT_STATE<=LAMP_TEST;
	LD_8888<='1';
        ELSIF SET_T='1' THEN
          NXT_STATE<=SET_CLOCK;
          LD_CLK<='1';
        ELSIF  ((START='1') AND (DONE='0')) THEN
          NXT_STATE<=TIMER;
          COOK<='1';
        END IF;
	WHEN TIMER=>
  IF DONE='1' THEN
          NXT_STATE<=DONE_MSG;
          LD_DONE<='1';
	ELSE
          NXT_STATE<=TIMER;
          COOK<='1';
        END IF;
	END CASE;
  END PROCESS;
END ARCHITECTURE ART;