de2_ltm_ephoto.tan.rpt

友晶科技提供的电子相册源代码

; Analyze latches as synchronous elements               ; On                 ;                 ;                          ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;                 ;                          ;             ;
; Enable Clock Latency                                  ; Off                ;                 ;                          ;             ;
; Number of source nodes to report per destination node ; 10                 ;                 ;                          ;             ;
; Number of destination nodes to report                 ; 10                 ;                 ;                          ;             ;
; Number of paths to report                             ; 200                ;                 ;                          ;             ;
; Report Minimum Timing Checks                          ; Off                ;                 ;                          ;             ;
; Use Fast Timing Models                                ; Off                ;                 ;                          ;             ;
; Report IO Paths Separately                            ; Off                ;                 ;                          ;             ;
; Cut Timing Path                                       ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe6|dffe7a  ; dcfifo_qlk1 ;
; Cut Timing Path                                       ; On                 ; rdptr_g         ; ws_dgrp|dffpipe9|dffe10a ; dcfifo_qlk1 ;
+-------------------------------------------------------+--------------------+-----------------+--------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 120.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 12                    ; 5                   ; -2.358 ns ;              ;
; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1 ;                    ; PLL output ; 120.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 12                    ; 5                   ; -5.275 ns ;              ;
; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2 ;                    ; PLL output ; 33.33 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 3                   ; -2.358 ns ;              ;
; CLOCK_50                                                                  ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP                                              ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                             ; To                                   ; From Clock                                                                ; To Clock                                                                  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
; -2.186 ns                               ; None                                                ; Reset_Delay:u8|oRST_0                                                                                                            ; Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                                                  ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0.974 ns                    ; 0.721 ns                  ; 2.907 ns                ;
; -2.186 ns                               ; None                                                ; Reset_Delay:u8|oRST_0                                                                                                            ; Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                                                  ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0.974 ns                    ; 0.721 ns                  ; 2.907 ns                ;
; -2.186 ns                               ; None                                                ; Reset_Delay:u8|oRST_0                                                                                                            ; Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                                                  ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0.974 ns                    ; 0.721 ns                  ; 2.907 ns                ;
; -2.114 ns                               ; None                                                ; Reset_Delay:u8|oRST_0                                                                                                            ; Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                                                  ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0.974 ns                    ; 0.733 ns                  ; 2.847 ns                ;
; -2.112 ns                               ; None                                                ; Reset_Delay:u8|oRST_0                                                                                                            ; Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                                                  ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0.974 ns                    ; 0.733 ns                  ; 2.845 ns                ;
; -2.112 ns                               ; None                                                ; Reset_Delay:u8|oRST_0                                                                                                            ; Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                                                  ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0.974 ns                    ; 0.733 ns                  ; 2.845 ns                ;
; -2.112 ns                               ; None                                                ; Reset_Delay:u8|oRST_0                                                                                                            ; Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                                                  ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0.974 ns                    ; 0.733 ns                  ; 2.845 ns                ;
; -2.112 ns                               ; None                                                ; Reset_Delay:u8|oRST_0                                                                                                            ; Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                                                  ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0.974 ns                    ; 0.733 ns                  ; 2.845 ns                ;