de2_ltm_ephoto.tan.rpt

友晶科技提供的电子相册源代码

without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Type                                                                                     ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                         ; To                                                                                                                                                           ; From Clock                                                                ; To Clock                                                                  ; Failed Paths ;
+------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Worst-case tsu                                                                           ; N/A       ; None                             ; 7.477 ns                         ; DRAM_DQ[7]                                                                                                                                                   ; Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Worst-case tco                                                                           ; N/A       ; None                             ; 13.031 ns                        ; adc_spi_controller:u2|oY_COORD[8]                                                                                                                            ; HEX2[2]                                                                                                                                                      ; CLOCK_50                                                                  ; --                                                                        ; 0            ;
; Worst-case tpd                                                                           ; N/A       ; None                             ; 8.340 ns                         ; KEY[0]                                                                                                                                                       ; GPIO_0[33]                                                                                                                                                   ; --                                                                        ; --                                                                        ; 0            ;
; Worst-case th                                                                            ; N/A       ; None                             ; 3.432 ns                         ; altera_internal_jtag                                                                                                                                         ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]                                                                                                                ; --                                                                        ; altera_internal_jtag~TCKUTAP                                              ; 0            ;
; Clock Setup: 'Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0' ; -2.186 ns ; 120.00 MHz ( period = 8.333 ns ) ; N/A                              ; Reset_Delay:u8|oRST_0                                                                                                                                        ; Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ; CLOCK_50                                                                  ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 86           ;
; Clock Setup: 'CLOCK_50'                                                                  ; 6.731 ns  ; 50.00 MHz ( period = 20.000 ns ) ; 152.95 MHz ( period = 6.538 ns ) ; lcd_spi_cotroller:u1|m3wire_data[14]                                                                                                                         ; lcd_spi_cotroller:u1|three_wire_controller:u0|mSDATA                                                                                                         ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2' ; 22.273 ns ; 33.33 MHz ( period = 30.000 ns ) ; 129.42 MHz ( period = 7.727 ns ) ; lcd_timing_controller:u6|y_cnt[2]                                                                                                                            ; Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|a_graycounter_o96:rdptr_g1p|counter_ffa[9]                ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2 ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                                              ; N/A       ; None                             ; 131.51 MHz ( period = 7.604 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5]                                                                                                           ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                                             ; altera_internal_jtag~TCKUTAP                                              ; altera_internal_jtag~TCKUTAP                                              ; 0            ;
; Clock Hold: 'CLOCK_50'                                                                   ; -2.579 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; touch_point_detector:u3|photo_cnt[1]~_Duplicate_2                                                                                                            ; flash_to_sdram_controller:u4|d1_photo_num[1]                                                                                                                 ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 15           ;
; Clock Hold: 'Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'  ; 0.391 ns  ; 120.00 MHz ( period = 8.333 ns ) ; N/A                              ; Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2'  ; 0.513 ns  ; 33.33 MHz ( period = 30.000 ns ) ; N/A                              ; Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe6|dffe7a[8] ; Sdram_Control_4Port:u7|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_qlk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe6|dffe8a[8] ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2 ; Sdram_Control_4Port:u7|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2 ; 0            ;
; Total number of failed paths                                                             ;           ;                                  ;                                  ;                                                                                                                                                              ;                                                                                                                                                              ;                                                                           ;                                                                           ; 101          ;
+------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                              ;
+-------------------------------------------------------+--------------------+-----------------+--------------------------+-------------+
; Option                                                ; Setting            ; From            ; To                       ; Entity Name ;
+-------------------------------------------------------+--------------------+-----------------+--------------------------+-------------+
; Device Name                                           ; EP2C35F672C6       ;                 ;                          ;             ;
; Timing Models                                         ; Final              ;                 ;                          ;             ;
; Default hold multicycle                               ; Same as Multicycle ;                 ;                          ;             ;
; Cut paths between unrelated clock domains             ; On                 ;                 ;                          ;             ;
; Cut off read during write signal paths                ; On                 ;                 ;                          ;             ;
; Cut off feedback from I/O pins                        ; On                 ;                 ;                          ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;                 ;                          ;             ;
; Ignore Clock Settings                                 ; Off                ;                 ;                          ;             ;