📄 dds.rpt
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Project Information e:\dds\dds.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/04/2007 09:33:14
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
dds EPM7032LC44-6 3 24 0 24 0 75 %
User Pins: 3 24 0
Project Information e:\dds\dds.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'colred16' is stuck at VCC
Warning: Primitive 'colred15' is stuck at VCC
Warning: Primitive 'colred11' is stuck at GND
Warning: Primitive 'colred10' is stuck at VCC
Warning: Primitive 'colred9' is stuck at VCC
Warning: Primitive 'colred8' is stuck at VCC
Warning: Primitive 'colred7' is stuck at VCC
Warning: Primitive 'colred6' is stuck at GND
Warning: Primitive 'colred3' is stuck at GND
Warning: Primitive 'colred2' is stuck at VCC
Warning: Primitive 'colred1' is stuck at VCC
Device-Specific Information: e:\dds\dds.rpt
dds
***** Logic for device 'dds' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
i i i
n n n
p p p
u u u
t t t
c c c r r
l l l V G G G G G o o
k k k C N N N N N w w
2 1 0 C D D D D D 4 3
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
colred9 | 7 39 | colred12
colred10 | 8 38 | colred13
colred11 | 9 37 | row2
GND | 10 36 | row1
colred8 | 11 35 | VCC
colred7 | 12 EPM7032LC44-6 34 | row5
colred6 | 13 33 | row8
colred16 | 14 32 | colred2
VCC | 15 31 | colred3
colred15 | 16 30 | GND
RESERVED | 17 29 | row7
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V c r c c c
E E E E N C o o o o o
S S S S D C l w l l l
E E E E r 6 r r r
R R R R e e e e
V V V V d d d d
E E E E 1 5 1 4
D D D D 4
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\dds\dds.rpt
dds
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 8/16( 50%) 11/16( 68%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 16/16(100%) 16/16(100%) 0/16( 0%) 3/36( 8%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 27/32 ( 84%)
Total logic cells used: 24/32 ( 75%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 24/32 ( 75%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 1.58
Total fan-in: 38
Total input pins required: 3
Total output pins required: 24
Total bidirectional pins required: 0
Total logic cells required: 24
Total flipflops required: 0
Total product terms required: 29
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\dds\dds.rpt
dds
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 13 0 inputclk0
5 (2) (A) INPUT 0 0 0 0 0 13 0 inputclk1
6 (3) (A) INPUT 0 0 0 0 0 12 0 inputclk2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\dds\dds.rpt
dds
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
27 29 B OUTPUT t 0 0 0 0 0 0 0 colred1
32 25 B OUTPUT t 0 0 0 0 0 0 0 colred2
31 26 B OUTPUT t 0 0 0 0 0 0 0 colred3
28 28 B OUTPUT t 0 0 0 3 0 0 0 colred4
26 30 B OUTPUT t 0 0 0 3 0 0 0 colred5
13 9 A OUTPUT t 0 0 0 0 0 0 0 colred6
12 8 A OUTPUT t 0 0 0 0 0 0 0 colred7
11 7 A OUTPUT t 0 0 0 0 0 0 0 colred8
7 4 A OUTPUT t 0 0 0 0 0 0 0 colred9
8 5 A OUTPUT t 0 0 0 0 0 0 0 colred10
9 6 A OUTPUT t 0 0 0 0 0 0 0 colred11
39 19 B OUTPUT t 0 0 0 3 0 0 0 colred12
38 20 B OUTPUT t 0 0 0 2 0 0 0 colred13
24 32 B OUTPUT t 0 0 0 3 0 0 0 colred14
16 11 A OUTPUT t 0 0 0 0 0 0 0 colred15
14 10 A OUTPUT t 0 0 0 0 0 0 0 colred16
36 22 B OUTPUT t 0 0 0 3 0 0 0 row1
37 21 B OUTPUT t 0 0 0 3 0 0 0 row2
40 18 B OUTPUT t 0 0 0 3 0 0 0 row3
41 17 B OUTPUT t 0 0 0 3 0 0 0 row4
34 23 B OUTPUT t 0 0 0 3 0 0 0 row5
25 31 B OUTPUT t 0 0 0 3 0 0 0 row6
29 27 B OUTPUT t 0 0 0 3 0 0 0 row7
33 24 B OUTPUT t 0 0 0 3 0 0 0 row8
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\dds\dds.rpt
dds
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC9 colred6
| +------------- LC8 colred7
| | +----------- LC7 colred8
| | | +--------- LC4 colred9
| | | | +------- LC5 colred10
| | | | | +----- LC6 colred11
| | | | | | +--- LC11 colred15
| | | | | | | +- LC10 colred16
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B | Logic cells that feed LAB 'A':
Pin
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\dds\dds.rpt
dds
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
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