📄 dds_graphic.rpt
字号:
Project Information e:\dds\dds_graphic.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/04/2007 10:16:47
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
dds_graphic
EP1K30TC144-1 1 40 0 0 0 % 60 3 %
User Pins: 1 40 0
Project Information e:\dds\dds_graphic.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
dds_graphic@55 clk
dds_graphic@88 green1
dds_graphic@114 green2
dds_graphic@98 green3
dds_graphic@90 green4
dds_graphic@87 green5
dds_graphic@89 green6
dds_graphic@95 green7
dds_graphic@99 green8
dds_graphic@36 green9
dds_graphic@33 green10
dds_graphic@29 green11
dds_graphic@31 green12
dds_graphic@30 green13
dds_graphic@63 green14
dds_graphic@68 green15
dds_graphic@73 green16
dds_graphic@80 red1
dds_graphic@100 red2
dds_graphic@102 red3
dds_graphic@96 red4
dds_graphic@83 red5
dds_graphic@91 red6
dds_graphic@97 red7
dds_graphic@101 red8
dds_graphic@32 red9
dds_graphic@27 red10
dds_graphic@65 red11
dds_graphic@81 red12
dds_graphic@28 red13
dds_graphic@70 red14
dds_graphic@79 red15
dds_graphic@78 red16
dds_graphic@51 row1
dds_graphic@59 row2
dds_graphic@60 row3
dds_graphic@48 row4
dds_graphic@46 row5
dds_graphic@43 row6
dds_graphic@41 row7
dds_graphic@38 row8
Project Information e:\dds\dds_graphic.rpt
** FILE HIERARCHY **
|dds:1|
|select:2|
|count:6|
|count:6|lpm_counter:lpm_counter_component|
|count:6|lpm_counter:lpm_counter_component|f8count:p8c1|
|count:6|lpm_counter:lpm_counter_component|f8count:p8c0|
|counter2:8|
|counter2:8|lpm_counter:lpm_counter_component|
|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|
|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|
Device-Specific Information: e:\dds\dds_graphic.rpt
dds_graphic
***** Logic for device 'dds_graphic' compiled without errors.
Device: EP1K30TC144-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S V S S S S S S S g S S S S S
E E E E E E E E E V E E E E E C E E E E E E E V r E E E E E
R R R R R R R R R C R R R R R C R R R R R R R C e R R R R R
V V V V V G V V V V C V V V V G V I G G G G V V V V V V V C e V V V V V
E E E E E N E E E E I E E E E N E N N N N N E E E E E E E I n E E E E E
D D D D D D D D D D O D D D D D D T D D D D D D D D D D D O 2 D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
RESERVED | 7 102 | red3
RESERVED | 8 101 | red8
RESERVED | 9 100 | red2
RESERVED | 10 99 | green8
RESERVED | 11 98 | green3
RESERVED | 12 97 | red7
RESERVED | 13 96 | red4
RESERVED | 14 95 | green7
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | red6
RESERVED | 19 EP1K30TC144-1 90 | green4
RESERVED | 20 89 | green6
RESERVED | 21 88 | green1
RESERVED | 22 87 | green5
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
RESERVED | 26 83 | red5
red10 | 27 82 | RESERVED
red13 | 28 81 | red12
green11 | 29 80 | red1
green13 | 30 79 | red15
green12 | 31 78 | red16
red9 | 32 77 | ^MSEL0
green10 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
green9 | 36 73 | green16
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R r R G r R r R V r R r R V r G V G c G G G r r V R g R r G R g R r V R
E o E N o E o E C o E o E C o N C N l N N N o o C E r E e N E r E e C E
S w S D w S w S C w S w S C w D C D k D D D w w C S e S d D S e S d C S
E 8 E 7 E 6 E I 5 E 4 E I 1 _ _ 2 3 I E e E 1 E e E 1 I E
R R R R O R R N C C O R n R 1 R n R 4 O R
V V V V V V T K K V 1 V V 1 V V
E E E E E E L L E 4 E E 5 E E
D D D D D D K K D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\dds\dds_graphic.rpt
dds_graphic
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
C5 4/ 8( 50%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
C7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C16 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
D2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
D4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
D6 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
D9 7/ 8( 87%) 4/ 8( 50%) 5/ 8( 62%) 1/2 0/2 1/22( 4%)
D12 8/ 8(100%) 6/ 8( 75%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
D14 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
E20 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
E23 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
E28 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
E30 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
E31 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
E33 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
F1 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 0/2 0/2 4/22( 18%)
F36 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 40/96 ( 41%)
Total logic cells used: 60/1728 ( 3%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.40/4 ( 85%)
Total fan-in: 204/6912 ( 2%)
Total input pins required: 1
Total input I/O cell registers required: 0
Total output pins required: 40
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 60
Total flipflops required: 21
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 6/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 4 0 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7/0
D: 0 1 0 1 0 8 0 0 7 0 0 8 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 1 0 8 0 0 0 13/0
F: 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 11/0
Total: 8 1 0 1 4 8 1 0 7 0 0 8 0 4 0 2 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 1 0 8 0 0 3 60/0
Device-Specific Information: e:\dds\dds_graphic.rpt
dds_graphic
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G ^ 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -