dds.tdf

使用VHDL硬件描述语言实现了直接频率合成器的制作

SUBDESIGN dds
(
	inputclk[2..0]	: INPUT ;
	row[8..1]   	: OUTPUT;
	colred[16..1]	: output;
)
BEGIN
%print out OK%
TABLE
inputclk[2..0]  =>	row[8..1],	colred[16..1];
  H"0"			=>	H"1", 		H"DBC3";            %1101 1011 1100 0011%
  H"1"		    =>  H"2",		H"EBDB";
  H"2"			=>  H"4",		H"EBDB";
  H"3"			=>  H"8",		H"F3DB";
  H"4"			=>  H"10",		H"F3DB";
  H"5"   		=>  H"20",		H"EBDB";
  H"6"			=>  H"40",      H"EBDB";
  H"7"			=>  H"80",		H"DBC3";
end table;
end;