📄 select.rpt
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Project Information e:\dds\select.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/04/2007 09:34:03
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
select EPM7064LC68-7 17 32 0 32 0 50 %
User Pins: 17 32 0
Device-Specific Information: e:\dds\select.rpt
select
***** Logic for device 'select' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: e:\dds\select.rpt
select
** ERROR SUMMARY **
Info: Chip 'select' in device 'EPM7064LC68-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
D D D D
A A A A
T T T T
D D V D A A A A
D D D A A C A O O V O O
A A A T T C T U U C U U
T T T G A A I G G G A G T T C T T
A A A N 1 1 N N N N 1 N 1 0 I 0 0
7 8 9 D 6 5 T D D D 4 D 3 2 O 3 4
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
DATA6 | 10 60 | DATAOUT05
VCCIO | 11 59 | DATAOUT06
DATA5 | 12 58 | GND
DATA4 | 13 57 | DATAOUT12
DATA3 | 14 56 | DATAOUT11
DATA2 | 15 55 | DATAOUT01
GND | 16 54 | DATAOUT14
DATA1 | 17 53 | VCCIO
SEL | 18 EPM7064LC68-7 52 | DATAOUT16
DATAOUT014 | 19 51 | DATAOUT15
DATAOUT116 | 20 50 | DATAOUT07
VCCIO | 21 49 | DATAOUT08
DATAOUT115 | 22 48 | GND
DATAOUT114 | 23 47 | DATAOUT09
DATAOUT113 | 24 46 | DATAOUT010
DATAOUT016 | 25 45 | DATAOUT011
GND | 26 44 | DATAOUT012
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
D D D D V D D G V D D G D D D D V
A A A A C A A N C A A N A A A A C
T T T T C T T D C T T D T T T T C
A A A A I A A I A A A A A A I
1 1 1 1 O O O N O O O O O O O
0 1 2 3 U U T U U U U U U
T T T T T T T T
0 0 1 1 1 1 1 1
1 1 7 8 9 1 1 1
3 5 0 1 2
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\dds\select.rpt
select
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 8/16( 50%) 12/12(100%) 0/16( 0%) 5/36( 13%)
C: LC33 - LC48 12/16( 75%) 12/12(100%) 0/16( 0%) 7/36( 19%)
D: LC49 - LC64 12/16( 75%) 12/12(100%) 0/16( 0%) 7/36( 19%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 48/48 (100%)
Total logic cells used: 32/64 ( 50%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 32/64 ( 50%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 2.00
Total fan-in: 64
Total input pins required: 17
Total output pins required: 32
Total bidirectional pins required: 0
Total logic cells required: 32
Total flipflops required: 0
Total product terms required: 48
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: e:\dds\select.rpt
select
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
17 (3) (A) INPUT 0 0 0 0 0 2 0 DATA1
15 (4) (A) INPUT 0 0 0 0 0 2 0 DATA2
14 (5) (A) INPUT 0 0 0 0 0 2 0 DATA3
13 (6) (A) INPUT 0 0 0 0 0 2 0 DATA4
12 (8) (A) INPUT 0 0 0 0 0 2 0 DATA5
10 (9) (A) INPUT 0 0 0 0 0 2 0 DATA6
9 (11) (A) INPUT 0 0 0 0 0 2 0 DATA7
8 (12) (A) INPUT 0 0 0 0 0 2 0 DATA8
7 (13) (A) INPUT 0 0 0 0 0 2 0 DATA9
27 (24) (B) INPUT 0 0 0 0 0 2 0 DATA10
28 (22) (B) INPUT 0 0 0 0 0 2 0 DATA11
29 (21) (B) INPUT 0 0 0 0 0 2 0 DATA12
30 (20) (B) INPUT 0 0 0 0 0 2 0 DATA13
67 - - INPUT 0 0 0 0 0 2 0 DATA14
4 (16) (A) INPUT 0 0 0 0 0 2 0 DATA15
5 (14) (A) INPUT 0 0 0 0 0 2 0 DATA16
18 (1) (A) INPUT 0 0 0 0 0 32 0 SEL
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\dds\select.rpt
select
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
55 53 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT01
64 62 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT02
62 61 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT03
61 60 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT04
60 59 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT05
59 57 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT06
50 48 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT07
49 46 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT08
47 45 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT09
46 44 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT010
45 43 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT011
56 54 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT11
44 41 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT012
57 56 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT12
32 19 B OUTPUT t 0 0 0 2 0 0 0 DATAOUT013
65 64 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT13
19 32 B OUTPUT t 0 0 0 2 0 0 0 DATAOUT014
54 52 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT14
33 17 B OUTPUT t 0 0 0 2 0 0 0 DATAOUT015
51 49 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT15
25 25 B OUTPUT t 0 0 0 2 0 0 0 DATAOUT016
52 51 D OUTPUT t 0 0 0 2 0 0 0 DATAOUT16
36 33 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT17
37 35 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT18
39 36 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT19
40 37 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT110
41 38 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT111
42 40 C OUTPUT t 0 0 0 2 0 0 0 DATAOUT112
24 27 B OUTPUT t 0 0 0 2 0 0 0 DATAOUT113
23 28 B OUTPUT t 0 0 0 2 0 0 0 DATAOUT114
22 29 B OUTPUT t 0 0 0 2 0 0 0 DATAOUT115
20 30 B OUTPUT t 0 0 0 2 0 0 0 DATAOUT116
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\dds\select.rpt
select
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------- LC19 DATAOUT013
| +------------- LC32 DATAOUT014
| | +----------- LC17 DATAOUT015
| | | +--------- LC25 DATAOUT016
| | | | +------- LC27 DATAOUT113
| | | | | +----- LC28 DATAOUT114
| | | | | | +--- LC29 DATAOUT115
| | | | | | | +- LC30 DATAOUT116
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'B'
LC | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
Pin
30 -> * - - - * - - - | - * - - | <-- DATA13
67 -> - * - - - * - - | - * - - | <-- DATA14
4 -> - - * - - - * - | - * - - | <-- DATA15
5 -> - - - * - - - * | - * - - | <-- DATA16
18 -> * * * * * * * * | - * * * | <-- SEL
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\dds\select.rpt
select
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------- LC48 DATAOUT07
| +--------------------- LC46 DATAOUT08
| | +------------------- LC45 DATAOUT09
| | | +----------------- LC44 DATAOUT010
| | | | +--------------- LC43 DATAOUT011
| | | | | +------------- LC41 DATAOUT012
| | | | | | +----------- LC33 DATAOUT17
| | | | | | | +--------- LC35 DATAOUT18
| | | | | | | | +------- LC36 DATAOUT19
| | | | | | | | | +----- LC37 DATAOUT110
| | | | | | | | | | +--- LC38 DATAOUT111
| | | | | | | | | | | +- LC40 DATAOUT112
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
9 -> * - - - - - * - - - - - | - - * - | <-- DATA7
8 -> - * - - - - - * - - - - | - - * - | <-- DATA8
7 -> - - * - - - - - * - - - | - - * - | <-- DATA9
27 -> - - - * - - - - - * - - | - - * - | <-- DATA10
28 -> - - - - * - - - - - * - | - - * - | <-- DATA11
29 -> - - - - - * - - - - - * | - - * - | <-- DATA12
67 -> - - - - - - - - - - - - | - * - - | <-- DATA14
18 -> * * * * * * * * * * * * | - * * * | <-- SEL
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\dds\select.rpt
select
** LOGIC CELL INTERCONNECTIONS **
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