digital_clk_hier_info

该工程的主要功能是由VHDL语言实现多功能数字电子时钟

|digital_clk
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8]~0.CLK
clk => count[7]~1.CLK
clk => i63.CLK
clk => i65.CLK
clk => i67.CLK
clk => i69.CLK
clk => i71.CLK
clk => i73.CLK
clk => i75.CLK
clk => clk1khz.CLK
clr => state[1].ACLR
clr => state[0].ACLR
clr => i982.IN0
clr => i984.IN0
clr => i988.IN0
clr => i992.IN0
clr => i996.IN0
clr => i1000.IN0
clr => i1004.IN0
clr => i1008.IN0
clr => i1012.IN0
clr => i1016.IN0
clr => i1020.IN0
clr => i1024.IN0
clr => i1028.IN0
clr => i1032.IN0
clr => i1036.IN0
clr => i1040.IN0
clr => i1044.IN0
clr => hour[3].ACLR
clr => hour[2].ACLR
clr => hour[1].ACLR
clr => hour[0].ACLR
clr => min[5].ACLR
clr => min[4].ACLR
clr => min[3].ACLR
clr => min[2].ACLR
clr => min[1].ACLR
clr => min[0].ACLR
clr => sec[5].ACLR
clr => sec[4].ACLR
clr => sec[3].ACLR
clr => sec[2].ACLR
clr => sec[1].ACLR
clr => sec[0].ACLR
clr => i980.IN0
clr => state[2].ACLR
clr => i986.IN0
clr => i990.IN0
clr => i994.IN0
clr => i998.IN0
clr => i1002.IN0
clr => i1006.IN0
clr => i1010.IN0
clr => i1014.IN0
clr => i1018.IN0
clr => i1022.IN0
clr => i1026.IN0
clr => i1030.IN0
clr => i1034.IN0
clr => i1038.IN0
clr => i1042.IN0
clr => i1046.IN0
clr => hour[4].ACLR
en => hour_display[4].ENA
en => hour_display[3].ENA
en => hour_display[2].ENA
en => hour_display[1].ENA
en => hour_display[0].ENA
en => min_display[5].ENA
en => min_display[4].ENA
en => min_display[3].ENA
en => min_display[2].ENA
en => min_display[1].ENA
en => min_display[0].ENA
en => sec_display[5].ENA
en => sec_display[4].ENA
en => sec_display[3].ENA
en => sec_display[2].ENA
en => sec_display[1].ENA
en => sec_display[0].ENA
en => hour[4].ENA
en => hour[3].ENA
en => hour[2].ENA
en => hour[1].ENA
en => hour[0].ENA
en => min[5].ENA
en => min[4].ENA
en => min[3].ENA
en => min[2].ENA
en => min[1].ENA
en => min[0].ENA
en => sec[5].ENA
en => sec[4].ENA
en => sec[3].ENA
en => sec[2].ENA
en => sec[1].ENA
en => sec[0].ENA
set12 => i724.OUTPUTSELECT
set12 => i725.OUTPUTSELECT
set12 => i726.OUTPUTSELECT
set12 => i727.OUTPUTSELECT
set12 => i728.OUTPUTSELECT
clken => i292.OUTPUTSELECT
mode => state[1].CLK
mode => state[0].CLK
mode => state[2].CLK
inc => i312.OUTPUTSELECT
inc => i313.OUTPUTSELECT
inc => i314.OUTPUTSELECT
inc => i315.OUTPUTSELECT
inc => i316.OUTPUTSELECT
inc => i339.OUTPUTSELECT
inc => i340.OUTPUTSELECT
inc => i341.OUTPUTSELECT
inc => i342.OUTPUTSELECT
inc => i343.OUTPUTSELECT
inc => i344.OUTPUTSELECT
inc => i366.OUTPUTSELECT
inc => i367.OUTPUTSELECT
inc => i368.OUTPUTSELECT
inc => i369.OUTPUTSELECT
inc => i370.OUTPUTSELECT
inc => i371.OUTPUTSELECT
inc => i447.OUTPUTSELECT
inc => i448.OUTPUTSELECT
inc => i449.OUTPUTSELECT
inc => i450.OUTPUTSELECT
inc => i451.OUTPUTSELECT
inc => i452.OUTPUTSELECT
inc => i524.OUTPUTSELECT
inc => i525.OUTPUTSELECT
inc => i526.OUTPUTSELECT
inc => i527.OUTPUTSELECT
inc => i528.OUTPUTSELECT
inc => i529.OUTPUTSELECT
clk_out <= clock.DB_MAX_OUTPUT_PORT_TYPE
seg7[0] <= i~80.DB_MAX_OUTPUT_PORT_TYPE
seg7[1] <= i~79.DB_MAX_OUTPUT_PORT_TYPE
seg7[2] <= i~78.DB_MAX_OUTPUT_PORT_TYPE
seg7[3] <= i~77.DB_MAX_OUTPUT_PORT_TYPE
seg7[4] <= i~76.DB_MAX_OUTPUT_PORT_TYPE
seg7[5] <= i~75.DB_MAX_OUTPUT_PORT_TYPE
seg7[6] <= i~74.DB_MAX_OUTPUT_PORT_TYPE
seg7[7] <= i~73.DB_MAX_OUTPUT_PORT_TYPE
scan[0] <= i~71.DB_MAX_OUTPUT_PORT_TYPE
scan[1] <= i~70.DB_MAX_OUTPUT_PORT_TYPE
scan[2] <= i~69.DB_MAX_OUTPUT_PORT_TYPE
scan[3] <= i~68.DB_MAX_OUTPUT_PORT_TYPE
scan[4] <= i~67.DB_MAX_OUTPUT_PORT_TYPE
scan[5] <= i~66.DB_MAX_OUTPUT_PORT_TYPE