digital_clk.tan.rpt

该工程的主要功能是由VHDL语言实现多功能数字电子时钟

; Device name                                           ; EPF10K10LC84-3     ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Ignore user-defined clock settings                    ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack ; Required Time ; Actual Time                                    ; From            ; To                                                           ;
+------------------------+-------+---------------+------------------------------------------------+-----------------+--------------------------------------------------------------+
; Worst-case tsu         ; N/A   ; None          ; 9.800 ns                                       ; clr             ; lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|q[0] ;
; Worst-case tco         ; N/A   ; None          ; 57.100 ns                                      ; hour_display[3] ; seg7[6]                                                      ;
; Worst-case tpd         ; N/A   ; None          ; 36.300 ns                                      ; set12           ; seg7[6]                                                      ;
; Worst-case th          ; N/A   ; None          ; 7.300 ns                                       ; inc             ; inc_reg                                                      ;
; Worst-case minimum tco ; N/A   ; None          ; 13.000 ns                                      ; cnt[0]          ; scan[1]                                                      ;
; Worst-case minimum tpd ; N/A   ; None          ; 25.100 ns                                      ; set12           ; seg7[1]                                                      ;
; Clock Setup: 'clk'     ; N/A   ; None          ; 55.25 MHz ( period = 18.100 ns )               ; sec[4]          ; min[2]                                                       ;
; Clock Setup: 'mode'    ; N/A   ; None          ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; state[2]        ; state[1]                                                     ;
+------------------------+-------+---------------+------------------------------------------------+-----------------+--------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; mode            ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                           ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack                                   ; Actual fmax (period)                                       ; From                                                       ; To                                                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+------------------------------------------------------------+--------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 55.25 MHz ( period = 18.100 ns )                           ; sec[4]                                                     ; min[4]                                                       ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 55.25 MHz ( period = 18.100 ns )                           ; sec[4]                                                     ; min[2]                                                       ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 56.18 MHz ( period = 17.800 ns )                           ; sec[4]                                                     ; sec[5]                                                       ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 56.18 MHz ( period = 17.800 ns )                           ; sec[4]                                                     ; sec[4]                                                       ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 56.18 MHz ( period = 17.800 ns )                           ; sec[4]                                                     ; sec[3]                                                       ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 56.18 MHz ( period = 17.800 ns )                           ; sec[4]                                                     ; sec[2]                                                       ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 57.47 MHz ( period = 17.400 ns )                           ; min[0]                                                     ; hour[4]                                                      ; clk        ; clk      ; None                        ; None                      ; None                    ;