digital_clk.txt

该工程的主要功能是由VHDL语言实现多功能数字电子时钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity digital_clk is
    port(clk:in std_logic;
         clr:in std_logic;
         en :in std_logic;
         set12:in std_logic;
         mode :in std_logic;--模式选择
         inup,indown:in std_logic;--置数
         clk_out:out std_logic;--闹钟
         seg7:out std_logic_vector(7 downto 0);
         scan: out std_logic_vector(5 downto 0));
end;
 
architecture one of digital_clk is
   signal state:integer range 0 to 5;--定义五种状态
   signal qhh,qhl,qmh,qml,qsh,qsl:std_logic_vector(3 downto 0);--小时‘分’秒的高位和低位
   signal data:std_logic_vector(3 downto 0);
   signal cnt:integer range 0 to 5;--扫描数码管的计数器
   signal clk1khz,clk1hz,clk2hz:std_logic;--1KH、1HZ、2KZ分频信号
   signal blink:std_logic_vector(2 downto 0);--闪烁信号
   signal  clock:std_logic;
   signal sec,min:integer range 0 to 59;
   signal hour:integer range  0 to 23;
begin

process(clk)--1KHZ分频 用于扫描数码管地址
   variable count :integer range 0 to 9999;
begin
   if clk'event and clk='1' then 
      if count =9999 then clk1khz<= not clk1khz;count:=0;
      else count:=count+1; 
      end if;
   end if;
end process;

process(clk1khz) --1HZ 用于计时
 variable count:integer range 0 to 499;
begin
  if clk1khz'event and clk1khz='1' then 
      if count =499 then clk1hz<= not clk1hz;count:=0;
      else count:=count+1; 
      end if;
  end if;
end process;

process(clk1khz)--2HZ用于闪烁
variable count:integer range 0 to 249;
begin
  if clk1khz'event and clk1khz='1' then 
      if count =249 then clk2hz<= not clk2hz;count:=0;
      else count:=count+1; 
      end if; 
  end if;
end process;

process(mode,clr)--模式转换
begin 
  if clr='1' then 
     state<=0;
  elsif mode'event and mode='1' then
        state<=state+1;
        if state=5 then state<=0;end if;
  end if;
end process;


process(clk1hz,state,en,clr,hour,sec,min,set12)--状态控制
variable hhtemp,mmtemp:integer range  0 to 59;
begin
  if en='1' then
     hour<=hour;
     min<=min;
     sec<=sec;
  elsif clr='1' then
        hour<=0;
        min<=0;
        sec<=0;
  elsif clk1hz'event and clk1hz='1' then
        case state is
             when 0=>if sec=59 then sec<=0;--模式0，正常计数
                           if min=59 then min<=0;
                              if hour=23 then hour<=0;
                              else hour<=hour+1;end if;
                           else min<=min+1;end if;
                        else sec<=sec+1;end if;
                        if min=mmtemp then 
                           if hour=hhtemp then clock<='1';end if;
                        else clock<='0';end if;
                        
             when 1=>if inup'event and inup='1' then--小时的校时
                           if hour=23 then hour<=0;
                           else hour<=hour+1; 
                           end if;
                        end if;
             when 2=>if inup'event and inup='1' then--分的校时
                           if min=59 then min<=0;
                           else min<=min+1; 
                           end if;
                        end if;
             when 3=>if inup'event and inup='1' then--秒的校时
                           if sec=23 then sec<=0;
                           else sec<=sec+1; 
                           end if;
                        end if;
             when 4=>if inup'event and inup='1' then--闹钟分的设定
                              if min=59 then min<=0;
                              else min<=min+1;end if;
                         end if;
                     mmtemp:=min;
             when 5=>if inup'event and inup='1' then--闹钟时的设定
                        if hour=23 then hour<=0;
                        else hour<=hour+1;end if;
                     end if;
                      hhtemp:=hour;
        end case ;
end if;
end process;
-------------------------设定时间时，令数码管闪烁--------------

process(state,clk2hz)
begin
   case state is
        when 0=> blink<="000";
        when 1=> blink<=(2=>clk2hz,others=>'0');
        when 2=> blink<=(1=>clk2hz,others=>'0');
        when 3=> blink<=(0=>clk2hz,others=>'0'); 
        when 4=> blink<=(1=>clk2hz,others=>'0');
        when 5=> blink<=(2=>clk2hz,others=>'0');
   end case;
end process;


--------------------秒的十进制转BCD----------------------------
process(sec)
begin
case sec is
     when 0|10|20|30|40|50  =>qsl<="0000";
     when 1|11|21|31|41|51  =>qsl<="0001";
     when 2|12|22|32|42|52  =>qsl<="0010";
     when 3|13|23|33|43|53  =>qsl<="0011";
     when 4|14|24|34|44|54  =>qsl<="0100";
     when 5|15|25|35|45|55  =>qsl<="0101"; 
     when 6|16|26|36|46|56  =>qsl<="0110"; 
     when 7|17|27|37|47|57  =>qsl<="0111";
     when 8|18|28|38|48|58  =>qsl<="1000";
     when 9|19|29|39|49|59  =>qsl<="1001"; 
     when others =>null;
end case;
case sec is
     when 0|1|2|3|4|5|6|7|8|9 =>qsh<="0000";
     when 10|11|12|13|14|15|16|17|18|19 =>qsh<="0001";
     when 20|21|22|23|24|25|26|27|28|29 =>qsh<="0010";
     when 30|31|32|33|34|35|36|37|38|39 =>qsh<="0011";
     when 40|41|42|43|44|45|46|47|48|49 =>qsh<="0100";
     when 50|51|52|53|54|55|56|57|58|59 =>qsh<="0101";
     when others=>null;
end case;
end process;


------------------ 分的十进制转BCD-----------------------------------
process(min)
begin
case min is
     when 0|10|20|30|40|50  =>qml<="0000";
     when 1|11|21|31|41|51  =>qml<="0001";
     when 2|12|22|32|42|52  =>qml<="0010";
     when 3|13|23|33|43|53  =>qml<="0011";
     when 4|14|24|34|44|54  =>qml<="0100";
     when 5|15|25|35|45|55  =>qml<="0101"; 
     when 6|16|26|36|46|56  =>qml<="0110"; 
     when 7|17|27|37|47|57  =>qml<="0111";
     when 8|18|28|38|48|58  =>qml<="1000";
     when 9|19|29|39|49|59  =>qml<="1001"; 
     when others =>null;
end case;
case min is
     when 0|1|2|3|4|5|6|7|8|9 =>qmh<="0000";
     when 10|11|12|13|14|15|16|17|18|19 =>qmh<="0001";
     when 20|21|22|23|24|25|26|27|28|29 =>qmh<="0010";
     when 30|31|32|33|34|35|36|37|38|39 =>qmh<="0011";
     when 40|41|42|43|44|45|46|47|48|49 =>qmh<="0100";
     when 50|51|52|53|54|55|56|57|58|59 =>qmh<="0101";
     when others=>null;
end case;
end process;


 

-----------------小时的十进制转换BCD--------------------------
process(hour)
variable htemp:integer range  0 to 23;
begin
   htemp:=hour;
   if htemp>12 then 
      if set12='1' then htemp:=htemp mod 12;end if;
   end if;
case htemp is
     when 0|10|20 =>qhl<="0000";
     when 1|11|21 =>qhl<="0001";           
     when 2|12|22 =>qhl<="0010";
     when 3|13|23 =>qhl<="0011";
     when 4|14=>qhl<="0100";
     when 5|15=>qhl<="0101";
     when 6|16=>qhl<="0110";
     when 7|17=>qhl<="0111";
     when 8|18=>qhl<="1000";
     when 9|19=>qhl<="1001";
     when others=>null;
end case;
case htemp is
     when 0|1|2|3|4|5|6|7|8|9 =>qhh<="0000";
     when 10|11|12|13|14|15|16|17|18|19 =>qhh<="0001";
     when 20|21|22|23=>qhh<="0010";
     when others =>null;
end case;
end process;
---------------------数码管动态扫描计数-----------------------------------
process(clk1khz)
begin
if clk1khz'event and clk1khz='1' then 
   if cnt =5 then cnt<=0;
   else cnt<=cnt+1;
   end if;
end if;
end process;
---------------------数码管动态扫描-----------------------------------------
process(cnt,qhh,qhl,qmh,qml,qsh,qsl,blink)
begin
case cnt is
     when 0 =>data<=qsl or(blink(0)&blink(0)&blink(0)&blink(0)); scan<="000001";
     when 1 =>data<=qsh or(blink(0)&blink(0)&blink(0)&blink(0)); scan<="000010";
     when 2 =>data<=qml or(blink(1)&blink(1)&blink(1)&blink(1)); scan<="000100";
     when 3 =>data<=qmh or(blink(1)&blink(1)&blink(1)&blink(1)); scan<="001000";
     when 4 =>data<=qhl or(blink(2)&blink(2)&blink(2)&blink(2)); scan<="010000";
     when 5 =>data<=qhh or(blink(2)&blink(2)&blink(2)&blink(2)); scan<="100000";
     when others=>null;
end case;
end process;
     


process(data,cnt)
begin
  case data is
     when "0000"=> case cnt is
                        when 2|4 =>seg7<="11111101";
                        when 0|1|3|5=>seg7<="11111100";
                   end case;
     when "0001"=> case cnt is
                        when 2|4 =>seg7<="01100001";
                        when 0|1|3|5=>seg7<="01100000";
                   end case;
     when "0010"=>case cnt is
                        when 2|4 =>seg7<="11011011";
                        when 0|1|3|5=>seg7<="11011010";
                   end case;
     when "0011"=> case cnt is
                        when 2|4 =>seg7<="11110011";
                        when 0|1|3|5=>seg7<="11110010";
                   end case;
	 when "0100"=> 
	               case cnt is
                        when 2|4 =>seg7<="01100111";
                        when 0|1|3|5=>seg7<="01100110";
                   end case;
	 when "0101"=> 
	                case cnt is
                        when 2|4 =>seg7<="10110111";
                        when 0|1|3|5=>seg7<="10110110";
                   end case;
	 when "0110"=> 
	               case cnt is
                        when 2|4 =>seg7<="10111111";
                        when 0|1|3|5=>seg7<="10111110";
                   end case;
	 when "0111"=> 
	               case cnt is
                        when 2|4 =>seg7<="11100001";
                        when 0|1|3|5=>seg7<="11100000";
                   end case;
     when "1000"=> 
                   case cnt is
                        when 2|4 =>seg7<="11111111";
                        when 0|1|3|5=>seg7<="11111110";
                   end case;
     when "1001"=> 
                   case cnt is
                        when 2|4 =>seg7<="11110111";
                        when 0|1|3|5=>seg7<="11110110";
                   end case;
     when others=>null;
end case;
end process;
clk_out<=clock;
end ;