digital_clk.tan.summary

该工程的主要功能是由VHDL语言实现多功能数字电子时钟

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 9.800 ns
From           : clr
To             : lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|q[0]

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 57.100 ns
From           : hour_display[3]
To             : seg7[6]

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 36.300 ns
From           : set12
To             : seg7[6]

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 7.300 ns
From           : inc
To             : inc_reg

Type           : Worst-case minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.000 ns
From           : cnt[0]
To             : scan[1]

Type           : Worst-case minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 25.100 ns
From           : set12
To             : seg7[1]

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 55.25 MHz ( period = 18.100 ns )
From           : sec[4]
To             : min[2]

Type           : Clock Setup: 'mode'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 125.00 MHz ( period = 8.000 ns )
From           : state[2]
To             : state[1]

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