digital_clk.map.rpt

该工程的主要功能是由VHDL语言实现多功能数字电子时钟

+-------------------------------+-------------+
; Logic cells                   ; 271         ;
; Total combinational functions ; 263         ;
; Total registers               ; 87          ;
; I/O pins                      ; 22          ;
; Maximum fan-out node          ; clk1hz      ;
; Maximum fan-out               ; 48          ;
; Total fan-out                 ; 1010        ;
; Average fan-out               ; 3.45        ;
+-------------------------------+-------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+-----------------------------------------------------------------
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 59    ;
; Number of synthesis-generated cells                    ; 212   ;
; Number of WYSIWYG LUTs                                 ; 59    ;
; Number of synthesis-generated LUTs                     ; 204   ;
; Number of WYSIWYG registers                            ; 42    ;
; Number of synthesis-generated registers                ; 45    ;
; Number of cells with combinational logic only          ; 184   ;
; Number of cells with registers only                    ; 8     ;
; Number of cells with combinational logic and registers ; 79    ;
+--------------------------------------------------------+-------+


+----------------------------------------------+
; General Register Statistics                  ;
+-----------------------------------------------
; Statistic                            ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR       ; 42    ;
; Number of registers using SLOAD      ; 2     ;
; Number of registers using ACLR       ; 20    ;
; Number of registers using ALOAD      ; 17    ;
; Number of registers using CLK_ENABLE ; 50    ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Tue Dec 02 14:32:47 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off digital_clk -c digital_clk
Info: Found 2 design units and 1 entities in source file digital_clk.vhd
    Info: Found design unit 1: digital_clk-one
    Info: Found entity 1: digital_clk
Warning: VHDL Process Statement warning at digital_clk.vhd(76): signal hour_display is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(77): signal min_display is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(78): signal sec_display is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(83): signal hour is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(84): signal min is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at digital_clk.vhd(85): signal sec is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at digital_clk.vhd(205): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(214): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(233): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(242): OTHERS choice is never selected
Warning: VHDL Process Statement warning at digital_clk.vhd(255): signal set12 is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at digital_clk.vhd(268): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(274): OTHERS choice is never selected
Info: VHDL Case Statement information at digital_clk.vhd(296): OTHERS choice is never selected
Info: Inferred 5 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: hhtemp[0]~10
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: i109~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=14) from the following logic: i75~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: mmtemp[0]~12
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: count[0]~4
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/sign_div_unsign.tdf
    Info: Found entity 1: sign_div_unsign
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_u_div.tdf
    Info: Found entity 1: alt_u_div
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 2 buffer(s)
    Info: Ignored 2 SOFT buffer(s)
Warning: Ignored 5 CARRY_SUM primitives
    Warning: Ignored 1 CARRY_SUM primitives -- cannot place fan-in logic in single logic cell
        Warning: Can't place logic feeding CARRY_SUM primitive lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] in single logic cell
            Warning: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~18 of type CARRY_SUM
            Warning: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] of type CARRY_SUM
    Warning: Ignored 4 CARRY_SUM primitive(s) -- cannot place fan-out logic in single logic cell
        Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] into a single logic cell
            Warning: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~42 of type LUT
            Warning: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~43 of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~18 into a single logic cell
            Warning: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~43 of type LUT
            Warning: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~42 of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] into a single logic cell
            Warning: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~19 of type LUT
            Warning: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~20 of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] into a single logic cell
            Warning: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~12 of type LUT
            Warning: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~13 of type LUT
Info: Found the following redundant logic cells in design
    Info: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~41
    Info: Node lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~40
Info: Found the following redundant logic cells in design
    Info: Logic cell lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~40
    Info: Logic cell lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00011|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~41
Info: Implemented 293 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 15 output pins
    Info: Implemented 271 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Processing ended: Tue Dec 02 14:33:03 2008
    Info: Elapsed time: 00:00:15