husw.vhd

用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED."<=";



entity acsu is

    port (rst, clk, state_ini : in std_logic;
          -- sw : in std_logic ; -- switch butterfly
          cs_en : in std_logic ; -- compare enable for trellis initial state
          pre_pm0, pre_pm1 : in std_logic_vector(4 downto 0);
          bm0, bm1 : in std_logic_vector(1 downto 0);
          pm0, pm1 : out std_logic_vector(4 downto 0);
          db0, db1 : out std_logic); -- db is decision bit

end acsu;


architecture arch_acsu of acsu is

    component butterfly 
        
        port (state_ini : in std_logic;
              pre_pm0, pre_pm1 : in std_logic_vector(4 downto 0);
              bm0, bm1 : in std_logic_vector(1 downto 0);
              pm0_up, pm0_dw : out std_logic_vector(4 downto 0);
              pm1_up, pm1_dw : out std_logic_vector(4 downto 0));
    end component;

    -- signal --
    signal comp0up, comp0dw, comp1up, comp1dw : std_logic_vector(4 downto 0);
    signal pm0_temp, pm1_temp : std_logic_vector(4 downto 0);
    -- signal db0_temp, db1_temp : std_logic;
    -- signal en : std_logic;


    begin

    buff_comp : butterfly port map (state_ini=>state_ini, pre_pm0=>pre_pm0, pre_pm1=>pre_pm1,
                                    bm0=>bm0, bm1=>bm1, pm0_up=>comp0up, pm0_dw=>comp0dw,
                                    pm1_up=>comp1up, pm1_dw=>comp1dw);



    comp0 : 
        process(comp0up, comp0dw, cs_en)

        begin

            if comp0up > comp0dw and cs_en='0' then
                db0 <= '1';
                pm0_temp <= comp0dw;
            else
                db0 <= '0';
                pm0_temp <= comp0up;
            end if;

        end process;


    comp1 : 
        process(comp1up, comp1dw, cs_en)

        begin

            if comp1up > comp1dw and cs_en='0' then
                db1 <= '1';
                pm1_temp <= comp1dw;
            else
                db1 <= '0';
                pm1_temp <= comp1up;
            end if;

        end process;



    outff1 : 
        process(rst, clk)

        begin
            
            if rst = '1' then
                pm0 <= (others => '0');
            elsif clk'event and clk='1' then
                pm0 <= pm0_temp;
            end if;
        
        end process;


    
    outff2 : 
        process(rst, clk)

        begin
            
            if rst = '1' then
                pm1 <= (others => '0');
            elsif clk'event and clk='1' then
                pm1 <= pm1_temp;
            end if;
        
        end process;

end arch_acsu;