add.v

来自「cordic IC implement for fast cordic calc」· Verilog 代码 · 共 51 行

/**********************************************************************
*  Author      :   畗產狽(Shyu,Jia-jye)(ZYCA)
*  DATA        :   2004/10/22
*  FILE        :   add.v
*  VERSION     :   1
*  DESCRIPTION :   Adder for DSP IC.
*                  
*  VERSION NOTE:   1. Created @ 2004.10.22
**********************************************************************/

module          add( 
                     add_cin,
                     add_a,
                     add_b,
                     add_sum,
                     add_cout,
                     add_of
                     );
  
  parameter  W_DATA   = 8;
  
  input                        add_cin; //carry in
  input      [ W_DATA- 1: 0]   add_a;
  input      [ W_DATA- 1: 0]   add_b;
  
  output                       add_cout;//carry out
  output                       add_of;  //overflow flag
  output     [ W_DATA- 1: 0]   add_sum;
  
  wire                         add_cin; //carry in
  wire       [ W_DATA- 1: 0]   add_a;
  wire       [ W_DATA- 1: 0]   add_b;  
  wire                         add_cout;//carry out
  wire                         add_of;  //overflow flag
  wire       [ W_DATA- 1: 0]   add_sum;
  wire       [ W_DATA- 2: 0]   a_tmp;
  wire       [ W_DATA- 2: 0]   b_tmp;
  wire                         c_tmp;
  
  assign  a_tmp = add_a[ W_DATA- 2: 0];
  
  assign  b_tmp = add_b[ W_DATA- 2: 0];
  
  assign  { c_tmp, add_sum[ W_DATA- 2: 0]} = a_tmp + b_tmp + add_cin;
  
  assign  { add_cout, add_sum[ W_DATA- 1]} = add_a[ W_DATA- 1] + add_b[ W_DATA- 1] + c_tmp;
                               
  assign  add_of = c_tmp ^ add_cout;
  
  
endmodule