cordic.v

cordic IC implement for fast cordic calculate. Including test bench. feature: 1. slicon proved.

/**********************************************************************
*  Author      :   畗產狽(Shyu,Jia-jye)(ZYCA)
*  DATA        :   2004/11/17
*  FILE        :   cordic.v
*  VERSION     :   1
*  DESCRIPTION :   CORDIC.
*                  Coordinate rotation digital computer
*                  Note: the rotation angle clockwise is +
*                        counter clockwise is -
*                        different from the mathmatical caculation
*  VERSION NOTE:   1. Created @ 2004.11.17
*                  2. Modify defparam to verilog 2001. @2004.12.7
**********************************************************************/

module          cordic(
                        clk,
                        rst_n,
                        in_a,
                        in_b,
                        scal_f,
                        pass,
                        dir,
                        out_a,
                        out_b
                        );
  
  parameter  STAGE = 9; //CORDIC stages (n+1)
  parameter  W_DATA = 8;
  parameter  G_BITS = 3;//Guard bit size
  parameter  W_GUARD= W_DATA+ G_BITS;//data width with guard bits
  //parameter  SCALE_FACTOR = 11'b0100_1101_101;
  
  input                     clk;
  input                     rst_n;
  input    [ STAGE: 0]      pass; //Pass or not for each cordic stage
  input    [ STAGE: 0]      dir;  //Rotate direction for each stage
  input    [ W_DATA- 1: 0]  in_a;
  input    [ W_DATA- 1: 0]  in_b;
  input    [ W_GUARD- 1: 0] scal_f;//scale factor
  
  output   [ W_DATA- 1: 0]  out_a;
  output   [ W_DATA- 1: 0]  out_b;
  

/***********************************************************************
               Wire net declare
***********************************************************************/  
  wire     [ W_DATA- 1: 0]  st0_a;
  wire     [ W_DATA- 1: 0]  st0_b;
  
  wire     [ W_GUARD- 1: 0] st1_in_a;
  wire     [ W_GUARD- 1: 0] st1_in_b;
  wire     [ W_GUARD- 1: 0] st1_out_a;
  wire     [ W_GUARD- 1: 0] st1_out_b;
  wire     [ W_GUARD- 1: 0] st2_out_a;
  wire     [ W_GUARD- 1: 0] st2_out_b;
  wire     [ W_GUARD- 1: 0] st3_out_a;
  wire     [ W_GUARD- 1: 0] st3_out_b;
  wire     [ W_GUARD- 1: 0] st4_out_a;
  wire     [ W_GUARD- 1: 0] st4_out_b;
  wire     [ W_GUARD- 1: 0] st5_out_a;
  wire     [ W_GUARD- 1: 0] st5_out_b;
  wire     [ W_GUARD- 1: 0] st6_out_a;
  wire     [ W_GUARD- 1: 0] st6_out_b;
  wire     [ W_GUARD- 1: 0] st7_out_a;
  wire     [ W_GUARD- 1: 0] st7_out_b;
  wire     [ W_GUARD- 1: 0] st8_out_a;
  wire     [ W_GUARD- 1: 0] st8_out_b;
  wire     [ W_GUARD- 1: 0] st9_out_a;
  wire     [ W_GUARD- 1: 0] st9_out_b;
  
  //wire     [ W_GUARD- 1: 0] mul_a_in;
  //wire     [ W_GUARD- 1: 0] mul_b_in;
  
  wire     [ 2* W_GUARD- 1: 0] mul_a_out;
  wire     [ 2* W_GUARD- 1: 0] mul_b_out;
  
  wire     [ W_DATA- 1: 0]  out_a;
  wire     [ W_DATA- 1: 0]  out_b;
  wire     [ W_DATA- 1: 0]  out_a_wire;
  wire     [ W_DATA- 1: 0]  out_b_wire;
  
  wire     [ W_GUARD- 1: 0] scal_f;// scale factor
  
/***********************************************************************
              integer declare
***********************************************************************/    
  integer                   i;

/***********************************************************************
              Reg net declare
***********************************************************************/  
  
  reg      [ G_BITS- 1: 0]  a_sign;
  reg      [ G_BITS- 1: 0]  b_sign;
  
  
/**********************************************************************
               Continuous assignment
**********************************************************************/

  //Sign extension for guard bit
  //assign  st1_in_a = { G_BITS{ st0_a[W_DATA- 1]}, st0_a};
  //assign  st1_in_b = { G_BITS{ st0_b[W_DATA- 1]}, st0_b};
  assign  st1_in_a = { a_sign, st0_a};
  assign  st1_in_b = { b_sign, st0_b};
  
  //assign  out_a = ( mul_a_out[ 2* W_GUARD- 2: W_GUARD+ G_BITS- 1])<<G_BITS;
  //assign  out_b = ( mul_b_out[ 2* W_GUARD- 2: W_GUARD+ G_BITS- 1])<<G_BITS;
  assign  out_a_wire = ( mul_a_out[ 2* W_GUARD- 2: W_GUARD+ G_BITS- 1])<<G_BITS;
  assign  out_b_wire = ( mul_b_out[ 2* W_GUARD- 2: W_GUARD+ G_BITS- 1])<<G_BITS;
  //assign  scal_f = SCALE_FACTOR;
  
/**********************************************************************
               Sequencial assignment
**********************************************************************/
  always @( st0_a)
    for ( i= 0; i< G_BITS; i= i+ 1)
      a_sign[ i] =  st0_a[W_DATA- 1];
  
  always @( st0_b)
    for ( i= 0; i< G_BITS; i= i+ 1)
      b_sign[ i] =  st0_b[W_DATA- 1];

/**********************************************************************
               Component instantiate                                   
**********************************************************************/
  
  //stage 0 for +- pi/2
  rot_half_pi        
           #( 
              .W_DATA ( W_DATA) 
              ) 
    COR_0ST ( 
              .pass   ( pass[0]),
              .dir    ( dir[0]),
              .in_a   ( in_a),
              .in_b   ( in_b),
              .out_a  ( st0_a),
              .out_b  ( st0_b)
              );  
    
  //stage 1 for atan(2^0)  
  rot_angle_k       
           #(
              .W_DATA( W_GUARD),
              .SHIFT_K( 0),
              .W_SVAL( 4),
              .W_ADD_DATA( W_GUARD)
              ) 
    COR_1ST ( 
              .clk      ( clk),
              .rst_n    ( rst_n),
              .pass     ( pass[1]),
              .dir      ( dir[1]),
              .in_a     ( st1_in_a),
              .in_b     ( st1_in_b),
              .out_a    ( st1_out_a),
              .out_b    ( st1_out_b),
              .add_err  ( ) 
              );
  
  //stage 2 for atna(2^1)  
  rot_angle_k       
           #(
              .W_DATA( W_GUARD),
              .SHIFT_K( 1),
              .W_SVAL( 4),
              .W_ADD_DATA( W_GUARD)
              )  
    COR_2ST ( 
              .clk      ( clk),
              .rst_n    ( rst_n),
              .pass     ( pass[2]),
              .dir      ( dir[2]),
              .in_a     ( st1_out_a),
              .in_b     ( st1_out_b),
              .out_a    ( st2_out_a),
              .out_b    ( st2_out_b),
              .add_err  ( ) 
              );
  
  //stage 3 for atna(2^2)  
  rot_angle_k       
           #(
              .W_DATA( W_GUARD),
              .SHIFT_K( 2),
              .W_SVAL( 4),
              .W_ADD_DATA( W_GUARD)
              ) 
    COR_3ST (
              .clk      ( clk),
              .rst_n    ( rst_n),
              .pass     ( pass[3]),
              .dir      ( dir[3]),
              .in_a     ( st2_out_a),
              .in_b     ( st2_out_b),
              .out_a    ( st3_out_a),
              .out_b    ( st3_out_b),
              .add_err  ( ) 
              );
    
  //stage 4 for atna(2^3)  
  rot_angle_k       
           #(
              .W_DATA( W_GUARD),
              .SHIFT_K( 3),
              .W_SVAL( 4),
              .W_ADD_DATA( W_GUARD)
              ) 
    COR_4ST ( 
              .clk      ( clk),
              .rst_n    ( rst_n),
              .pass     ( pass[4]),
              .dir      ( dir[4]),
              .in_a     ( st3_out_a),
              .in_b     ( st3_out_b),
              .out_a    ( st4_out_a),
              .out_b    ( st4_out_b),
              .add_err  ( ) 
              );
    
  //stage 5 for atna(2^4)  
  rot_angle_k       
           #(
              .W_DATA( W_GUARD),
              .SHIFT_K( 4),
              .W_SVAL( 4),
              .W_ADD_DATA( W_GUARD)
              ) 
    COR_5ST (
              .clk      ( clk),
              .rst_n    ( rst_n),
              .pass     ( pass[5]),
              .dir      ( dir[5]),
              .in_a     ( st4_out_a),
              .in_b     ( st4_out_b),
              .out_a    ( st5_out_a),
              .out_b    ( st5_out_b),
              .add_err  ( ) 
              );
    
  //stage 6 for atna(2^5)  
  rot_angle_k       
           #(
              .W_DATA( W_GUARD),
              .SHIFT_K( 5),
              .W_SVAL( 4),
              .W_ADD_DATA( W_GUARD)
              ) 
    COR_6ST ( 
              .clk      ( clk),
              .rst_n    ( rst_n),
              .pass     ( pass[6]),
              .dir      ( dir[6]),
              .in_a     ( st5_out_a),
              .in_b     ( st5_out_b),
              .out_a    ( st6_out_a),
              .out_b    ( st6_out_b),
              .add_err  ( ) 
              );
    
  //stage 7 for atna(2^6)  
  rot_angle_k       
           #(
              .W_DATA( W_GUARD),
              .SHIFT_K( 6),
              .W_SVAL( 4),
              .W_ADD_DATA( W_GUARD)
              )  
    COR_7ST ( 
              .clk      ( clk),
              .rst_n    ( rst_n),
              .pass     ( pass[7]),
              .dir      ( dir[7]),
              .in_a     ( st6_out_a),
              .in_b     ( st6_out_b),
              .out_a    ( st7_out_a),
              .out_b    ( st7_out_b),
              .add_err  ( ) 
              );
    
  //stage 8 for atna(2^7)  
  rot_angle_k       
           #(
              .W_DATA( W_GUARD),
              .SHIFT_K( 7),
              .W_SVAL( 4),
              .W_ADD_DATA( W_GUARD)
              )  
    COR_8ST ( 
              .clk      ( clk),
              .rst_n    ( rst_n),
              .pass     ( pass[8]),
              .dir      ( dir[8]),
              .in_a     ( st7_out_a),
              .in_b     ( st7_out_b),
              .out_a    ( st8_out_a),
              .out_b    ( st8_out_b),
              .add_err  ( ) 
              );
    
  //stage 9 for atna(2^8)  
  rot_angle_k       
           #(
              .W_DATA( W_GUARD),
              .SHIFT_K( 8),
              .W_SVAL( 4),
              .W_ADD_DATA( W_GUARD)
              )  
    COR_9ST ( 
              .clk      ( clk),
              .rst_n    ( rst_n),
              .pass     ( pass[9]),
              .dir      ( dir[9]),
              .in_a     ( st8_out_a),
              .in_b     ( st8_out_b),
              .out_a    ( st9_out_a),
              .out_b    ( st9_out_b),
              .add_err  ( ) 
              );
    
  mul         
         #(
            .W_DATA( W_GUARD)
            )
    MUL_A ( 
            .ma   ( st9_out_a), 
            .mx   ( scal_f), 
            .mp   ( mul_a_out)
            ); 
    
  mul         
         #(
            .W_DATA( W_GUARD)
            ) 
    MUL_B ( 
            .ma   ( st9_out_b), 
            .mx   ( scal_f), 
            .mp   ( mul_b_out)
            ); 
    
  dffreg      
             #(
                .W_DATA( W_DATA)
                )
    DFF_OUT_A (
                .clk    ( clk),
                .rst_n  ( rst_n),
                .set_n  ( 1'b1),
                .en     ( 1'b1),
                .din    ( out_a_wire),
                .qout   ( out_a)
                );
                        
  dffreg      
             #(
                .W_DATA( W_DATA)
                )
    DFF_OUT_B (
                .clk    ( clk),
                .rst_n  ( rst_n),
                .set_n  ( 1'b1),
                .en     ( 1'b1),
                .din    ( out_b_wire),
                .qout   ( out_b)
                );
                        
     
endmodule