mul.v

来自「cordic IC implement for fast cordic calc」· Verilog 代码 · 共 31 行

/**********************************************************************
*  Author      :   畗產狽(Shyu,Jia-jye)(ZYCA)
*  DATA        :   2004/10/22
*  FILE        :   mul.v
*  VERSION     :   1
*  DESCRIPTION :   Multiplier for DSP IC.
*                  
*  VERSION NOTE:   1. Created @ 2004.10.22
**********************************************************************/

module          mul( 
                     ma, 
                     mx, 
                     mp
                     );
                     
  parameter   W_DATA    = 8;
  parameter   W_MP  = 2 * W_DATA;
  
  input       [ W_DATA- 1: 0]   ma;
  input       [ W_DATA- 1: 0]   mx;
  
  output      [ W_MP- 1: 0]     mp;
  
  wire signed [ W_MP- 1: 0]     mp;
  wire signed [ W_DATA- 1: 0]   ma;
  wire signed [ W_DATA- 1: 0]   mx;
  
  assign  mp = mx * ma;
    
endmodule