cordic_tp.v

cordic IC implement for fast cordic calculate. Including test bench. feature: 1. slicon proved.

/**********************************************************************
*  Author      :   畗產狽(Shyu,Jia-jye)(ZYCA)
*  DATA        :   2004/11/17
*  FILE        :   cordic_tp.v
*  VERSION     :   1
*  DESCRIPTION :   Test pattern for CORDIC.
*                  
*  VERSION NOTE:   1. Created @ 2004.11.17
**********************************************************************/

`timescale  1ns/100ps

module          cordic_tp(
                           clk,
                           rst_n,
                           in_a,
                           in_b,
                           scal_f,
                           pass,
                           dir
                           );
  
  parameter  STAGE = 9; //CORDIC stages (n+1)
  parameter  W_DATA = 8;
  parameter  G_BITS = 3;//Guard bit size
  parameter  W_GUARD= W_DATA+ G_BITS;//data width with guard bits
  parameter  tCLK   = 10.0;
  parameter  PAT_NUM = 4;
  parameter  W_ADDR  = 2;
                           
  output                   clk;
  output                   rst_n;
  
  output  [ W_DATA- 1: 0]  in_a;
  output  [ W_DATA- 1: 0]  in_b;
  output  [ W_GUARD- 1: 0] scal_f;
  
  output  [ STAGE: 0]      pass;
  output  [ STAGE: 0]      dir;
  
  reg                      clk;
  reg                      rst_n;
  reg     [ W_DATA- 1: 0]  in_a;
  reg     [ W_DATA- 1: 0]  in_b;  
  reg     [ STAGE: 0]      pass;
  reg     [ STAGE: 0]      dir;
  reg     [ W_GUARD- 1: 0] scal_f;
  
  
  
  //Data ROM code
  reg     [ W_DATA- 1: 0]    rom_in_a[ 0: PAT_NUM- 1];
  
  wire    [ W_ADDR- 1: 0]    in_a_addr;
  wire    [ W_DATA- 1: 0]    in_a_code;
  
  reg     [ W_DATA- 1: 0]    rom_in_b[ 0: PAT_NUM- 1];
  
  wire    [ W_ADDR- 1: 0]    in_b_addr;
  wire    [ W_DATA- 1: 0]    in_b_code;
  
  //Pass ROM code
  reg     [ STAGE: 0]        rom_pass[ 0: PAT_NUM- 1];
                             
  wire    [ W_ADDR- 1: 0]    pass_addr;
  wire    [ STAGE: 0]        pass_code;
                             
  //Dir ROM code             
  reg     [ STAGE: 0]        rom_dir[ 0: PAT_NUM- 1];
                             
  wire    [ W_ADDR- 1: 0]    dir_addr;
  wire    [ STAGE: 0]        dir_code;
                             
  //Scale factor code        
  reg     [ W_GUARD- 1: 0]   rom_scal[ 0: PAT_NUM- 1];
                             
  wire    [ W_ADDR- 1: 0]    scal_addr;
  wire    [ W_GUARD- 1: 0]   scal_code;
                             
  //Reg for counter          
  reg     [ W_ADDR- 1: 0]    cnt, cnt_n;
                             
  //Reg for delay pass       
  reg     [ STAGE: 0]        pass9;
  reg     [ STAGE- 1: 0]     pass8;
  reg     [ STAGE- 2: 0]     pass7;
  reg     [ STAGE- 3: 0]     pass6;
  reg     [ STAGE- 4: 0]     pass5;
  reg     [ STAGE- 5: 0]     pass4;
  reg     [ STAGE- 6: 0]     pass3;
  reg     [ STAGE- 7: 0]     pass2;
  reg     [ STAGE- 8: 0]     pass1;
  reg                        pass0;
                             
  //Reg for delay dir        
  reg     [ STAGE: 0]        dir9;
  reg     [ STAGE- 1: 0]     dir8;
  reg     [ STAGE- 2: 0]     dir7;
  reg     [ STAGE- 3: 0]     dir6;
  reg     [ STAGE- 4: 0]     dir5;
  reg     [ STAGE- 5: 0]     dir4;
  reg     [ STAGE- 6: 0]     dir3;
  reg     [ STAGE- 7: 0]     dir2;
  reg     [ STAGE- 8: 0]     dir1;
  reg                        dir0;
  
  //Reg for delay scale factor
  reg     [ W_GUARD- 1: 0]   scal_d_reg[ 0: STAGE];
  
  //Reg for delay data output
  reg     [ W_DATA- 1: 0]    in_a_reg;
  reg     [ W_DATA- 1: 0]    in_b_reg;  
  
  integer                    i;

/**********************************************************************
               Trapzoidal delayed output pattern                                   
**********************************************************************/
  //Reg for delay data
  always @( negedge clk or negedge rst_n)
    if ( ! rst_n)
      for (i= 0; i< W_DATA; i= i+ 1)
      begin
        in_a[ i]     <= 1'b0;
        in_a_reg[ i] <= 1'b0;
      end
    else
      { in_a, in_a_reg} <= { in_a_reg, in_a_code};
      
  always @( negedge clk or negedge rst_n)
    if ( ! rst_n)
      for (i= 0; i< W_DATA; i= i+ 1)
      begin
        in_b[ i]     <= 1'b0;
        in_b_reg[ i] <= 1'b0;
      end
    else
      { in_b, in_b_reg} <= { in_b_reg, in_b_code};
    
  
  //Reg for delay pass
  always @( negedge clk or negedge rst_n)
    if ( ! rst_n)
    begin
    
      pass0 <= 0;
      pass1 <= 0;
      pass2 <= 0;
      pass3 <= 0;
      pass4 <= 0;
      pass5 <= 0;
      pass6 <= 0;
      pass7 <= 0;
      pass8 <= 0;
      pass9 <= 0;
      
    end
    else
    begin
      { pass[ 0], pass0} <= { pass0, pass_code[ 0]};
      { pass[ 1], pass1} <= { pass1, pass_code[ 1]};
      { pass[ 2], pass2} <= { pass2, pass_code[ 2]};
      { pass[ 3], pass3} <= { pass3, pass_code[ 3]};
      { pass[ 4], pass4} <= { pass4, pass_code[ 4]};
      { pass[ 5], pass5} <= { pass5, pass_code[ 5]};
      { pass[ 6], pass6} <= { pass6, pass_code[ 6]};
      { pass[ 7], pass7} <= { pass7, pass_code[ 7]};
      { pass[ 8], pass8} <= { pass8, pass_code[ 8]};
      { pass[ 9], pass9} <= { pass9, pass_code[ 9]};
    end
    
  
  //Reg for delay dir
  always @( negedge clk or negedge rst_n)
    if ( ! rst_n)
    begin
    
      dir0 <= 0;
      dir1 <= 0;
      dir2 <= 0;
      dir3 <= 0;
      dir4 <= 0;
      dir5 <= 0;
      dir6 <= 0;
      dir7 <= 0;
      dir8 <= 0;
      dir9 <= 0;
      
    end
    else
    begin
      { dir[ 0], dir0} <= { dir0, dir_code[ 0]};
      { dir[ 1], dir1} <= { dir1, dir_code[ 1]};
      { dir[ 2], dir2} <= { dir2, dir_code[ 2]};
      { dir[ 3], dir3} <= { dir3, dir_code[ 3]};
      { dir[ 4], dir4} <= { dir4, dir_code[ 4]};
      { dir[ 5], dir5} <= { dir5, dir_code[ 5]};
      { dir[ 6], dir6} <= { dir6, dir_code[ 6]};
      { dir[ 7], dir7} <= { dir7, dir_code[ 7]};
      { dir[ 8], dir8} <= { dir8, dir_code[ 8]};
      { dir[ 9], dir9} <= { dir9, dir_code[ 9]};
    end  
    
    //Reg for delay scale factor
    always @( negedge clk or negedge rst_n)
      if ( ! rst_n)
      begin
        scal_f <= 0;
        for ( i= 0; i<=STAGE; i= i+ 1)
          scal_d_reg[ i] <= 0;
      end
      
      else
      begin
        
        scal_f <= scal_d_reg[ STAGE];
        scal_d_reg [ 0] <= scal_code;
        for ( i= 1; i<=STAGE; i= i+ 1)
          scal_d_reg[ i] <= scal_d_reg[ i- 1];
      
      end
      
  
/**********************************************************************
               ROM code for input pattern                                   
**********************************************************************/
  //Data ROM code
  assign  in_a_code = rom_in_a[ in_a_addr];
  
  initial
  begin
    rom_in_a[ 0] = 8'b1100_0000;
    rom_in_a[ 1] = 8'b1100_0000;
    rom_in_a[ 2] = 8'b1100_0000;
    rom_in_a[ 3] = 8'b1100_0000;
  end
  
  assign  in_b_code = rom_in_b[ in_b_addr];
  
  initial
  begin
    rom_in_b[ 0] = 8'b0110_0000;
    rom_in_b[ 1] = 8'b0110_0000;
    rom_in_b[ 2] = 8'b0110_0000;
    rom_in_b[ 3] = 8'b0110_0000;
  end
  
  
  //Pass ROM code
  assign  pass_code = rom_pass[ pass_addr];
  
  initial
  begin
  
    rom_pass[ 0] = 10'b1101_0100_00;
    rom_pass[ 1] = 10'b1111_1111_10;
    rom_pass[ 2] = 10'b1111_1111_01;
    rom_pass[ 3] = 10'b1011_0110_11;
    
  end
    
  //Dir ROM code
  assign  dir_code = rom_dir[ dir_addr];
  
  initial
  begin
  
    rom_dir[ 0] = 10'b0000_0000_00;
    rom_dir[ 1] = 10'b0000_0000_00;
    rom_dir[ 2] = 10'b0000_0000_00;
    rom_dir[ 3] = 10'b0100_1000_00;
    
  end
  
  //Scale factor code
  assign  scal_code = rom_scal[ scal_addr];
  
  initial
  begin
  
    rom_scal[ 0] = 11'b010_0111_0010;
    rom_scal[ 1] = 11'b011_1111_1111;
    rom_scal[ 2] = 11'b010_1101_0100;
    rom_scal[ 3] = 11'b011_1001_0010;
    
  end


/**********************************************************************
               Address counter generation                                   
**********************************************************************/  
  
  //Create counter
  always @( negedge clk or negedge rst_n)
    if ( ! rst_n)
      cnt <= 0;
    else
      cnt <= cnt_n;
      
  always @( cnt)
    if ( cnt == 0)
      cnt_n <= 1;
    else if ( cnt == ( PAT_NUM- 1))
      cnt_n <= 0;
    else
      cnt_n <= cnt+ 1;
      
/**********************************************************************
               Continuous assignment for ROM address generation                                   
**********************************************************************/ 
  assign  scal_addr = cnt;
  assign  pass_addr = cnt;
  assign  dir_addr  = cnt;
  assign  in_a_addr = cnt;
  assign  in_b_addr = cnt;
  
/**********************************************************************
               MISC signal generation                                   
**********************************************************************/
  
  //Create clock
  always #( tCLK/2.0) clk = ~ clk;
    
  initial
  begin
    clk = 1'b0;
    rst_n = 1'b1;
    in_a = 8'b0;
    in_b = 8'b0;
    
    #20  rst_n = 1'b0;
    
    #20  rst_n = 1'b1;
    /*
         in_a = 8'b1100_0000;//-0.5
         in_b = 8'b0110_0000;//0.75i ans = 0.5000 - 0.7500i
    
         pass = 10'b1101_0100_00;//angle = pi u(i)=1,1,1,1,0,1,0,1,0,0 or -1,-1,-1,-1,0,-1,0,-1,0,0
         dir  = 10'b0000_0000_00;//angle = pi ,i = 0, 1,....,9         
         scal_f = 11'b010_0111_0010;//0.6123
         
    #110  pass = 10'b1111_1111_10;//angle=pi/2 u(i)=1,0,0,0,0,0,0,0,0,0
          dir  = 10'b0000_0000_00;//ans= -0.7500 - 0.5000i
          scal_f = 11'b011_1111_1111;//1 ~0.999999
         
    #110  pass = 10'b1111_1111_01;//angle = pi/4, u(i) = 0,1,0,0,0,0,0,0,0,0,0
          dir  = 10'b0000_0000_00;//ans = -0.8839 + 0.1768i
          scal_f = 11'b010_1101_0100;//0.7107
    
    #110  pass = 10'b1011_0110_11;// angle = pi/8 u(i) = 0,0,1,0,0,-1,0,0,-1,0
          dir  = 10'b0100_1000_00;//ans = -0.7490 + 0.5016i
          scal_f = 11'b011_1001_0010;//0.6123
    */
  end

endmodule