rot_angle_k.v

cordic IC implement for fast cordic calculate. Including test bench. feature: 1. slicon proved.

/**********************************************************************
*  Author      :   畗產狽(Shyu,Jia-jye)(ZYCA)
*  DATA        :   2004/11/17
*  FILE        :   rot_angle_k.v
*  VERSION     :   4
*  DESCRIPTION :   Rotate arctan2^-k fo CORDIC first stage.
*                  pass : 1'b1: u(i) = 0, 1'b0 u(i) != 0.
*                  dir : 1'b0: u(i)=1 1'b1: u(i)=-1.
*  VERSION NOTE:   1. Created @ 2004.11.17
*                  2. Make the rotataion sign the same as methmaticaly.
*                  3. Modify defparam to verilog 2001. @2004.12.7
*                  4. Re-coding for better architecture. @2004.12.10.
**********************************************************************/

module          rot_angle_k( 
                             clk,
                             rst_n,
                             pass,
                             dir,
                             in_a,
                             in_b,
                             out_a,
                             out_b,
                             add_err
                             );

  parameter  W_DATA = 11;
  parameter  SHIFT_K = 0;
  parameter  W_SVAL  = 4;
  parameter  W_ADD_DATA = 11;
  
  input                      clk;
  input                      rst_n;
  input                      pass;
  input                      dir;
  input    [ W_DATA- 1: 0]   in_a;
  input    [ W_DATA- 1: 0]   in_b;
  
  output                     add_err;
  output   [ W_DATA- 1: 0]   out_a;
  output   [ W_DATA- 1: 0]   out_b;
  
  wire                       add_a_of;
  wire                       add_b_of;
  wire                       sel_n;
  wire                       sel_p;
  wire                       add_err;
  wire     [ W_SVAL- 1: 0]   shift_val;
  wire     [ W_DATA- 1: 0]   a_wire;
  wire     [ W_DATA- 1: 0]   b_wire;
  wire     [ W_DATA- 1: 0]   a_sh_wire;
  wire     [ W_DATA- 1: 0]   b_sh_wire;
  wire     [ W_DATA- 1: 0]   add_a_wire;
  wire     [ W_DATA- 1: 0]   add_b_wire;
  wire     [ W_DATA- 1: 0]   out_a;
  wire     [ W_DATA- 1: 0]   out_b;
  wire     [ W_DATA- 1: 0]   add_a_in;
  wire     [ W_DATA- 1: 0]   add_b_in;

/**********************************************************************
               Continuous assignment
**********************************************************************/
  assign  shift_val = SHIFT_K;
  
  assign  add_err = add_a_of | add_b_of;
  
  assign  sel_n = ~ dir;
  assign  sel_p = dir;
  
  assign  out_a = ( pass)? a_wire: add_a_wire;
  assign  out_b = ( pass)? b_wire: add_b_wire;
  
  assign  add_a_in = { W_DATA{ sel_n}} ^ a_sh_wire;
  assign  add_b_in = { W_DATA{ sel_p}} ^ b_sh_wire;
  
/**********************************************************************
               Component instantiate
**********************************************************************/  
  dffreg 
           #(
              .W_DATA ( W_DATA)
              )     
    DFFREG_A(
              .clk    ( clk),
              .rst_n  ( rst_n),
              .set_n  ( 1'b1),
              .en     ( 1'b1),
              .din    ( in_a),
              .qout   ( a_wire)
              );
                        
  dffreg 
           #(
              .W_DATA ( W_DATA)
              )     
    DFFREG_B(
              .clk    ( clk),
              .rst_n  ( rst_n),
              .set_n  ( 1'b1),
              .en     ( 1'b1),
              .din    ( in_b),
              .qout   ( b_wire)
              );    
                        
  shfter   
         #(
            .W_DATA    ( W_DATA),
            .W_SVAL    ( W_SVAL)
            )  
    SHFT_A(
            .s_dir     ( 1'b0),
            .rot       ( 1'b0),
            .sign      ( 1'b1),
            .shft_val  ( shift_val),
            .d_in      ( b_wire),
            .q_out     ( a_sh_wire)                          
            );
  
  shfter   
         #(
            .W_DATA    ( W_DATA),
            .W_SVAL    ( W_SVAL)
            )  
    SHFT_B(
            .s_dir     ( 1'b0),
            .rot       ( 1'b0),
            .sign      ( 1'b1),
            .shft_val  ( shift_val),
            .d_in      ( a_wire),
            .q_out     ( b_sh_wire)                          
            );
  
  add         
        #(
           .W_DATA    ( W_ADD_DATA)
           )
    ADD_A( 
           .add_cin   ( sel_n),
           .add_a     ( a_wire),
           .add_b     ( add_a_in),
           .add_sum   ( add_a_wire),
           .add_cout  (),
           .add_of    ( add_a_of)
           );  
        
  add 
        #(
           .W_DATA    ( W_ADD_DATA)
           )        
    ADD_B( 
           .add_cin   ( sel_p),
           .add_a     ( add_b_in),
           .add_b     ( b_wire),
           .add_sum   ( add_b_wire),
           .add_cout  (),
           .add_of    ( add_b_of)
           );  
                   
endmodule