dffreg.v

来自「cordic IC implement for fast cordic calc」· Verilog 代码 · 共 46 行

/**********************************************************************
*  Author      :   畗產狽(Shyu,Jia-jye)(ZYCA)
*  DATA        :   2004/10/22
*  FILE        :   dffreg.v
*  VERSION     :   1
*  DESCRIPTION :   D-flipflop register for DSP IC.
*                  
*  VERSION NOTE:   1. Created @ 2004.10.22
**********************************************************************/

module          dffreg(
                        clk,
                        rst_n,
                        set_n,
                        en,
                        din,
                        qout
                        );
                        
  parameter  W_DATA = 8;
  
  input                     clk;
  input                     rst_n;
  input                     set_n;
  input                     en;
  input    [ W_DATA- 1: 0]  din;
  
  output   [ W_DATA- 1: 0]  qout;
  
  reg      [ W_DATA- 1: 0]  qout;
  
  integer                   i;
  
  always @( posedge clk or negedge rst_n or negedge set_n)
    if ( ! rst_n)
      for ( i= 0; i< W_DATA; i= i+ 1)
        qout[i] <= 1'b0;
    else if ( ! set_n)
      for ( i= 0; i< W_DATA; i= i+ 1)
        qout[i] <= 1'b1;
    else if ( en)
      qout <= din;
    else
      qout <= qout; 

endmodule