📄 display.rpt
字号:
# !_LC2_A23 & _LC3_A12 & !_LC6_A23;
-- Node name is ':3736'
-- Equation name is '_LC2_A7', type is buried
_LC2_A7 = LCELL( _EQ061);
_EQ061 = !_LC5_A24 & _LC7_A7
# _LC2_A18 & !_LC5_A24
# _LC5_A24 & _LC8_A7;
-- Node name is ':3739'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ062);
_EQ062 = _LC2_A7 & !_LC7_A24
# !hourhdis0 & !hourhdis1 & _LC7_A24;
-- Node name is '~3757~1'
-- Equation name is '~3757~1', location is LC7_A8, type is buried.
-- synthesized logic cell
_LC7_A8 = LCELL( _EQ063);
_EQ063 = !secldis0 & !secldis1 & !secldis2 & secldis3
# !secldis0 & secldis1 & secldis2 & !secldis3;
-- Node name is '~3757~2'
-- Equation name is '~3757~2', location is LC4_A8, type is buried.
-- synthesized logic cell
_LC4_A8 = LCELL( _EQ064);
_EQ064 = !_LC6_A8 & _LC7_A8
# _LC1_A8 & !_LC6_A8
# _LC5_A2;
-- Node name is '~3757~3'
-- Equation name is '~3757~3', location is LC6_A12, type is buried.
-- synthesized logic cell
_LC6_A12 = LCELL( _EQ065);
_EQ065 = !sechdis0 & sechdis1;
-- Node name is '~3757~4'
-- Equation name is '~3757~4', location is LC2_A13, type is buried.
-- synthesized logic cell
_LC2_A13 = LCELL( _EQ066);
_EQ066 = !_LC3_A24 & _LC4_A8
# _LC3_A24 & _LC6_A12
# _LC2_A12 & _LC3_A24;
-- Node name is '~3757~5'
-- Equation name is '~3757~5', location is LC3_A13, type is buried.
-- synthesized logic cell
_LC3_A13 = LCELL( _EQ067);
_EQ067 = !minldis0 & !minldis1 & !minldis2 & minldis3
# !minldis0 & minldis1 & minldis2 & !minldis3;
-- Node name is '~3757~6'
-- Equation name is '~3757~6', location is LC5_A13, type is buried.
-- synthesized logic cell
_LC5_A13 = LCELL( _EQ068);
_EQ068 = !_LC1_A13 & _LC3_A13
# !_LC1_A13 & _LC5_A16
# _LC3_A16;
-- Node name is '~3757~7'
-- Equation name is '~3757~7', location is LC6_A13, type is buried.
-- synthesized logic cell
_LC6_A13 = LCELL( _EQ069);
_EQ069 = _LC2_A13 & !_LC2_A23 & !_LC6_A23
# _LC2_A23 & _LC5_A13 & !_LC6_A23;
-- Node name is '~3757~8'
-- Equation name is '~3757~8', location is LC7_A13, type is buried.
-- synthesized logic cell
_LC7_A13 = LCELL( _EQ070);
_EQ070 = _LC6_A23 & !minhdis0 & !minhdis2
# _LC6_A23 & !minhdis0 & minhdis1;
-- Node name is '~3757~9'
-- Equation name is '~3757~9', location is LC8_A6, type is buried.
-- synthesized logic cell
_LC8_A6 = LCELL( _EQ071);
_EQ071 = !hourldis0 & !hourldis1 & !hourldis2 & hourldis3
# !hourldis0 & hourldis1 & hourldis2 & !hourldis3;
-- Node name is '~3757~10'
-- Equation name is '~3757~10', location is LC2_A6, type is buried.
-- synthesized logic cell
_LC2_A6 = LCELL( _EQ072);
_EQ072 = !_LC1_A4 & _LC8_A6
# !_LC1_A4 & _LC7_A6
# _LC3_A7;
-- Node name is '~3757~11'
-- Equation name is '~3757~11', location is LC8_A13, type is buried.
-- synthesized logic cell
_LC8_A13 = LCELL( _EQ073);
_EQ073 = !_LC5_A24 & _LC6_A13
# !_LC5_A24 & _LC7_A13
# _LC2_A6 & _LC5_A24;
-- Node name is ':3757'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = LCELL( _EQ074);
_EQ074 = !_LC7_A24 & _LC8_A13
# !hourhdis0 & _LC7_A24;
-- Node name is ':3763'
-- Equation name is '_LC8_A12', type is buried
_LC8_A12 = LCELL( _EQ075);
_EQ075 = _LC3_A8 & !_LC3_A24
# !_LC3_A24 & _LC5_A2
# _LC3_A24 & _LC4_A12;
-- Node name is ':3770'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = LCELL( _EQ076);
_EQ076 = _LC6_A23 & !minhdis0 & minhdis1
# _LC6_A23 & minhdis1 & !minhdis2
# _LC6_A23 & !minhdis0 & !minhdis2
# _LC6_A23 & minhdis0 & !minhdis1 & minhdis2;
-- Node name is ':3771'
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ077);
_EQ077 = _LC2_A4 & _LC2_A23 & !_LC6_A23
# !_LC2_A23 & !_LC6_A23 & _LC8_A12;
-- Node name is ':3772'
-- Equation name is '_LC8_A4', type is buried
_LC8_A4 = LCELL( _EQ078);
_EQ078 = _LC3_A4 & !_LC5_A24
# _LC4_A4 & !_LC5_A24
# _LC5_A24 & _LC7_A4;
-- Node name is ':3775'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = LCELL( _EQ079);
_EQ079 = !_LC7_A24 & _LC8_A4
# !hourhdis0 & _LC7_A24
# hourhdis1 & _LC7_A24;
-- Node name is ':3781'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = LCELL( _EQ080);
_EQ080 = !_LC1_A8 & !_LC3_A24
# !_LC3_A6 & _LC3_A24;
-- Node name is ':3788'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = LCELL( _EQ081);
_EQ081 = _LC6_A23 & !minhdis1
# _LC6_A23 & minhdis0
# _LC6_A23 & minhdis2;
-- Node name is ':3789'
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = LCELL( _EQ082);
_EQ082 = _LC2_A23 & !_LC5_A16 & !_LC6_A23
# !_LC2_A23 & _LC4_A6 & !_LC6_A23;
-- Node name is ':3790'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ083);
_EQ083 = _LC5_A6 & !_LC5_A24
# !_LC5_A24 & _LC6_A6
# _LC5_A24 & !_LC7_A6;
-- Node name is ':3793'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ084);
_EQ084 = _LC1_A6 & !_LC7_A24
# !hourhdis1 & _LC7_A24
# hourhdis0 & _LC7_A24;
-- Node name is ':3799'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ085);
_EQ085 = _LC3_A2 & !_LC3_A24
# _LC3_A24 & _LC6_A2
# _LC3_A24 & !_LC7_A2;
-- Node name is ':3806'
-- Equation name is '_LC5_A23', type is buried
_LC5_A23 = LCELL( _EQ086);
_EQ086 = _LC6_A23 & !minhdis2
# _LC6_A23 & minhdis0 & minhdis1
# _LC6_A23 & !minhdis0 & !minhdis1;
-- Node name is ':3807'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = LCELL( _EQ087);
_EQ087 = _LC2_A23 & _LC4_A16 & !_LC6_A23
# _LC1_A2 & !_LC2_A23 & !_LC6_A23;
-- Node name is ':3808'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = LCELL( _EQ088);
_EQ088 = _LC3_A23 & !_LC5_A24
# _LC5_A23 & !_LC5_A24
# _LC2_A9 & _LC5_A24;
-- Node name is ':3811'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = LCELL( _EQ089);
_EQ089 = _LC8_A23
# _LC7_A24;
-- Node name is ':3817'
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = LCELL( _EQ090);
_EQ090 = !_LC3_A24 & _LC5_A2
# !_LC3_A24 & _LC8_A2
# _LC3_A18 & _LC3_A24;
-- Node name is ':3820'
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = LCELL( _EQ091);
_EQ091 = _LC2_A23 & _LC3_A16
# _LC1_A16 & _LC2_A23
# !_LC2_A23 & _LC4_A18;
-- Node name is ':3823'
-- Equation name is '_LC8_A18', type is buried
_LC8_A18 = LCELL( _EQ092);
_EQ092 = _LC5_A18 & !_LC6_A23
# _LC6_A18 & _LC6_A23
# _LC6_A23 & _LC7_A18;
-- Node name is ':3826'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = LCELL( _EQ093);
_EQ093 = !_LC5_A24 & _LC8_A18
# _LC3_A7 & _LC5_A24
# _LC4_A7 & _LC5_A24;
-- Node name is ':3829'
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ094);
_EQ094 = _LC1_A18 & !_LC7_A24
# !hourhdis0 & _LC7_A24
# hourhdis1 & _LC7_A24;
-- Node name is ':3883'
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = LCELL( _EQ095);
_EQ095 = _LC7_A24
# !_LC5_A24 & _LC6_A23
# _LC3_A24 & !_LC5_A24;
Project Information d:\max+plus\display.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,808K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -