dds.syr

《Verilog-HDL实践与应用系统设计》一书中的光盘源文件

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : DDS.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : DDS
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : DDS
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : DDS.prj
Compiling included source file 'dds.v'
Module <DDS> compiled.
Module <CNT10> compiled.
Module <FULLADDER> compiled.
Module <R_SYDFF> compiled.
Module <F_ADDER> compiled.
Module <ADDER> compiled.
Continuing compilation of source file 'DDS.prj'
Compiling included source file 'd:/xilinx_webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'DDS.prj'
WARNING:Xst:1067 - dds.v Line 42. Port sizes don't match in port #3
WARNING:Xst:1067 - dds.v Line 45. Port sizes don't match in port #1
WARNING:Xst:1067 - dds.v Line 46. Port sizes don't match in port #1
WARNING:Xst:1067 - dds.v Line 47. Port sizes don't match in port #1
WARNING:Xst:1067 - dds.v Line 48. Port sizes don't match in port #1
WARNING:Xst:1067 - dds.v Line 49. Port sizes don't match in port #1
WARNING:Xst:1067 - dds.v Line 50. Port sizes don't match in port #1
WARNING:Xst:1067 - dds.v Line 51. Port sizes don't match in port #1
WARNING:Xst:1067 - dds.v Line 52. Port sizes don't match in port #1
9 warnings in compilation
No errors in compilation
Analysis of file <DDS.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing module <CNT10>.
Module <CNT10> is correct for synthesis.
 
Analyzing module <R_SYDFF>.
Module <R_SYDFF> is correct for synthesis.
 
Analyzing module <ADDER>.
Module <ADDER> is correct for synthesis.
 
Analyzing module <F_ADDER>.
Module <F_ADDER> is correct for synthesis.
 
Analyzing module <FULLADDER>.
Module <FULLADDER> is correct for synthesis.
 
Analyzing top module <DDS>.
Module <DDS> is correct for synthesis.

Synthesizing Unit <CNT10>.
    Related source file is dds.v.
    Found 4-bit up counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <CNT10> synthesized.


Synthesizing Unit <R_SYDFF>.
    Related source file is dds.v.
    Found 11-bit register for signal <Q>.
    Summary:
	inferred  11 D-type flip-flop(s).
Unit <R_SYDFF> synthesized.


Synthesizing Unit <ADDER>.
    Related source file is dds.v.
    Found 1-bit xor2 for signal <SUM>.
WARNING:Xst:647 - Input <A> is never used.
    Summary:
	inferred   1 Xor(s).
Unit <ADDER> synthesized.


Synthesizing Unit <F_ADDER>.
    Related source file is dds.v.
    Found 1-bit xor3 for signal <SUM>.
    Summary:
	inferred   1 Xor(s).
Unit <F_ADDER> synthesized.


Synthesizing Unit <FULLADDER>.
    Related source file is dds.v.
Unit <FULLADDER> synthesized.


Synthesizing Unit <DDS>.
    Related source file is dds.v.
Unit <DDS> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
  11-bit register                  : 1
# Counters                         : 1
  4-bit up counter                 : 1
# Xors                             : 11
  1-bit xor2                       : 1
  1-bit xor3                       : 10

=========================================================================


Starting low level synthesis...

Optimizing unit <CNT10> ...

Optimizing unit <F_ADDER> ...

Optimizing unit <ADDER> ...

Optimizing unit <FULLADDER> ...

Optimizing unit <R_SYDFF> ...

Optimizing unit <DDS> ...

Merging netlists...

=========================================================================
Final Results
Output File Name                   : DDS
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Xors                             : 24
  1-bit xor2                       : 24

Design Statistics
# Edif Instances                   : 111
# I/Os                             : 17

=========================================================================
CPU : 2.58 / 2.63 s | Elapsed : 3.00 / 3.00 s
 
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