dds.bld

来自「《Verilog-HDL实践与应用系统设计》一书中的光盘源文件」· BLD 代码 · 共 70 行

BLD
70 行
字号 
Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -uc DDS.ucf -p XC9500 DDS.ngc DDS.ngd Reading NGO file "E:/hdl/test/DDS.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor__n0000"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor__n0000 : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor_Result"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor_Result : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor__n0000"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor__n0000 : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor_Result"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor_Result : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor__n0000"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor__n0000 : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor_Result"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor_Result : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor__n0000"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor__n0000 : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor_Result"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor_Result : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor__n0000"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor__n0000 : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor_Result"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor_Result : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor__n0000"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor__n0000 : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor_Result"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor_Result : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor__n0000"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor__n0000 : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor_Result"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor_Result : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor__n0000"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor__n0000 : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor_Result"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor_Result : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor__n0000"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor__n0000 : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor_Result"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor_Result : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor__n0000"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor__n0000 : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM_Mxor_Result"...WARNING:LBEngine:353 - Module Mxor_SUM_Mxor_Result : All styles for SIMPLE_GATES
   are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Mxor_SUM"...WARNING:LBEngine:353 - Module Mxor_SUM : All styles for SIMPLE_GATES are
   implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Q_Madd__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module Q_Madd__n0000_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Q_Madd__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module Q_Madd__n0000_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Q_Madd__n0000_Mxor_Result_3"...WARNING:LBEngine:353 - Module Q_Madd__n0000_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Annotating constraints to design from file "DDS.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "DDS.ngd" ...Writing NGDBUILD log file "DDS.bld"...

dds.bld - 源码说明

本页面展示了「《Verilog-HDL实践与应用系统设计》一书中的光盘源文件」中的 dds.bld 源码文件，采用 BLD 编程语言编写，共 70 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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