📄 dds.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: DDS Date: 9-19-2002, 5:21PM
Device Used: XC9572-7-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
15 /72 ( 20%) 100 /360 ( 27%) 15 /72 ( 20%) 17 /34 ( 50%) 30 /144 ( 20%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 4 4 | I/O : 13 15
Output : 8 8 | GCK/IO : 1 2
Bidirectional : 4 4 | GTS/IO : 2 0
GCK : 1 1 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 17 17
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 15
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Signal 'CLK' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 15 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 15 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
DOUT<0> 3 3 FB2_2 STD FAST 35 I/O I/O
DOUT<10> 9 15 FB4_2 STD FAST 24 I/O O
DOUT<1> 5 5 FB2_11 STD FAST 40 GTS/I/O I/O
DOUT<2> 10 7 FB2_14 STD FAST 42 GTS/I/O I/O
DOUT<3> 9 8 FB4_17 STD FAST 34 I/O O
DOUT<4> 9 9 FB4_15 STD FAST 33 I/O O
DOUT<5> 9 10 FB4_14 STD FAST 29 I/O O
DOUT<6> 9 11 FB4_11 STD FAST 28 I/O O
DOUT<7> 9 12 FB4_9 STD FAST 27 I/O O
DOUT<8> 9 13 FB4_8 STD FAST 26 I/O O
DOUT<9> 9 14 FB4_5 STD FAST 25 I/O O
MCLK 3 5 FB1_5 STD FAST 2 I/O I/O
U3/Q_0 2 2 FB4_16 STD (b) (b)
U3/Q_1 3 5 FB4_1 STD (b) (b)
U3/Q_2 2 3 FB4_7 STD (b) (b)
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
CLK FB1_11 6 GCK/I/O GCK
DATA<0> FB1_15 8 I/O I
DATA<1> FB1_17 9 I/O I
DATA<2> FB2_9 39 GSR/I/O I
RB FB1_2 1 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 1 5 5 3 0/1 9
FB2 3 7 7 18 0/3 9
FB3 0 0 0 0 0/0 8
FB4 11 18 18 79 8/0 8
---- ----- ----- -----
15 100 8/4 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 5/31
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O I
(unused) 0 0 0 5 FB1_3 (b)
(unused) 0 0 0 5 FB1_4 (b)
MCLK 3 0 0 2 FB1_5 STD 2 I/O I/O
(unused) 0 0 0 5 FB1_6 3 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 4 I/O
(unused) 0 0 0 5 FB1_9 5 GCK/I/O
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 6 GCK/I/O GCK
(unused) 0 0 0 5 FB1_12 (b)
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 7 GCK/I/O
(unused) 0 0 0 5 FB1_15 8 I/O I
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 9 I/O I
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: N62.FBK.LFBK 3: "U3/Q_0" 5: "U3/Q_2"
2: RB 4: "U3/Q_1"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
MCLK XXXXX................................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 7/29
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
DOUT<0> 3 0 0 2 FB2_2 STD 35 I/O I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 36 I/O
(unused) 0 0 0 5 FB2_6 37 I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 38 I/O
(unused) 0 0 0 5 FB2_9 39 GSR/I/O I
(unused) 0 0 0 5 FB2_10 (b)
DOUT<1> 5 0 0 0 FB2_11 STD 40 GTS/I/O I/O
(unused) 0 0 0 5 FB2_12 (b)
(unused) 0 0 \/3 2 FB2_13 (b) (b)
DOUT<2> 10 5<- 0 0 FB2_14 STD 42 GTS/I/O I/O
(unused) 0 0 /\2 3 FB2_15 43 I/O (b)
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 44 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: MCLK.PIN 4: "DATA<2>" 6: "DATA<0>"
2: N51.FBK.LFBK 5: "DATA<1>" 7: RB
3: N53.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DOUT<0> X....XX................................. 3 3
DOUT<1> XX..XXX................................. 5 5
DOUT<2> XXXXXXX................................. 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 11 I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 12 I/O
(unused) 0 0 0 5 FB3_6 (b)
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 13 I/O
(unused) 0 0 0 5 FB3_9 14 I/O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 18 I/O
(unused) 0 0 0 5 FB3_12 (b)
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 19 I/O
(unused) 0 0 0 5 FB3_15 20 I/O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 22 I/O
(unused) 0 0 0 5 FB3_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 18/18
Number of signals used by logic mapping into function block: 18
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
U3/Q_1 3 0 0 2 FB4_1 STD (b) (b)
DOUT<10> 9 4<- 0 0 FB4_2 STD 24 I/O O
(unused) 0 0 /\4 1 FB4_3 (b) (b)
(unused) 0 0 \/2 3 FB4_4 (b) (b)
DOUT<9> 9 4<- 0 0 FB4_5 STD 25 I/O O
(unused) 0 0 /\2 3 FB4_6 (b) (b)
U3/Q_2 2 0 \/3 0 FB4_7 STD (b) (b)
DOUT<8> 9 4<- 0 0 FB4_8 STD 26 I/O O
DOUT<7> 9 5<- /\1 0 FB4_9 STD 27 I/O O
(unused) 0 0 /\5 0 FB4_10 (b) (b)
DOUT<6> 9 4<- 0 0 FB4_11 STD 28 I/O O
(unused) 0 0 /\4 1 FB4_12 (b) (b)
(unused) 0 0 \/5 0 FB4_13 (b) (b)
DOUT<5> 9 5<- \/1 0 FB4_14 STD 29 I/O O
DOUT<4> 9 4<- 0 0 FB4_15 STD 33 I/O O
U3/Q_0 2 0 /\3 0 FB4_16 STD (b) (b)
DOUT<3> 9 4<- 0 0 FB4_17 STD 34 I/O O
(unused) 0 0 /\4 1 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: "DOUT<0>".PIN 7: N57.FBK.LFBK 13: "DATA<1>"
2: "DOUT<1>".PIN 8: N58.FBK.LFBK 14: "DATA<0>"
3: "DOUT<2>".PIN 9: N59.FBK.LFBK 15: RB
4: MCLK.PIN 10: N60.FBK.LFBK 16: "U3/Q_0.FBK".LFBK
5: N55.FBK.LFBK 11: N61.FBK.LFBK 17: "U3/Q_1.FBK".LFBK
6: N56.FBK.LFBK 12: "DATA<2>" 18: "U3/Q_2.FBK".LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
U3/Q_1 ...X..........XXXX...................... 5 5
DOUT<10> XXXXXXXXXXXXXXX......................... 15 15
DOUT<9> XXXXXXXXXX.XXXX......................... 14 14
U3/Q_2 ..............XXX....................... 3 3
DOUT<8> XXXXXXXXX..XXXX......................... 13 13
DOUT<7> XXXXXXXX...XXXX......................... 12 12
DOUT<6> XXXXXXX....XXXX......................... 11 11
DOUT<5> XXXXXX.....XXXX......................... 10 10
DOUT<4> XXXXX......XXXX......................... 9 9
U3/Q_0 ..............XX........................ 2 2
DOUT<3> XXXX.......XXXX......................... 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"DOUT<0>".T = "DATA<0>"
"DOUT<0>".CLKF = MCLK.PIN
"DOUT<0>".RSTF = /RB
"DOUT<0>".PRLD = GND
"DOUT<10>".T = "DATA<2>" * N55.FBK.LFBK * N56.FBK.LFBK *
N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * N60.FBK.LFBK *
N61.FBK.LFBK * "DOUT<2>".PIN
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