dds.gyd

来自「《Verilog-HDL实践与应用系统设计》一书中的光盘源文件」· GYD 代码 · 共 39 行

Pin Freeze File:  version E.33

957244 XC9572-7-PC44
DATA<2> S:PIN39
DATA<1> S:PIN9
DATA<0> S:PIN8
RB S:PIN1
CLK S:PIN6
DOUT<0> S:PIN35
DOUT<10> S:PIN24
DOUT<1> S:PIN40
DOUT<2> S:PIN42
DOUT<3> S:PIN34
DOUT<4> S:PIN33
DOUT<5> S:PIN29
DOUT<6> S:PIN28
DOUT<7> S:PIN27
DOUT<8> S:PIN26
DOUT<9> S:PIN25
MCLK S:PIN2


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_5 N62

PARTITION FB2_2 N51
PARTITION FB2_11 N53
PARTITION FB2_13 EXP0_ N54 EXP1_


PARTITION FB4_1 "U3/Q_1" N52 EXP2_ EXP3_
		 N61 EXP4_ "U3/Q_2" N60
		 N59 EXP5_ N58 EXP6_
		 EXP7_ N57 N56 "U3/Q_0"
		 N55 EXP8_