dds.pnx

来自「《Verilog-HDL实践与应用系统设计》一书中的光盘源文件」· PNX 代码 · 共 18 行

<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
  arch   CDATA #REQUIRED
  device CDATA #REQUIRED
  spg    CDATA #REQUIRED
  pkg    CDATA #REQUIRED>
<!ATTLIST pin
  nm     CDATA #REQUIRED
  no     CDATA #REQUIRED
  iostd  (TTL|LVTTL|LVCMOS2|NA) "NA"
  sr     (SLOW|FAST|slow|fast) "SLOW">
]>
<ibis><part pkg="PC44" spg="-7" arch="xc9500" device="XC9572"/><pin nm="RB" no="1"/><pin nm="DATA&lt;0&gt;" no="8"/><pin nm="DATA&lt;1&gt;" no="9"/><pin nm="DATA&lt;2&gt;" no="39"/><pin nm="CLK" no="6"/><pin nm="DOUT&lt;3&gt;" no="34" sr="fast"/><pin nm="DOUT&lt;4&gt;" no="33" sr="fast"/><pin nm="DOUT&lt;5&gt;" no="29" sr="fast"/><pin nm="DOUT&lt;6&gt;" no="28" sr="fast"/><pin nm="DOUT&lt;7&gt;" no="27" sr="fast"/><pin nm="DOUT&lt;8&gt;" no="26" sr="fast"/><pin nm="DOUT&lt;9&gt;" no="25" sr="fast"/><pin nm="DOUT&lt;10&gt;" no="24" sr="fast"/><pin nm="DOUT&lt;1&gt;" no="40" sr="fast"/><pin nm="DOUT&lt;2&gt;" no="42" sr="fast"/><pin nm="DOUT&lt;0&gt;" no="35" sr="fast"/><pin nm="MCLK" no="2" sr="fast"/></ibis>