cnt4.syr

《Verilog-HDL实践与应用系统设计》一书中的光盘源文件

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : CNT4.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : CNT4
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : CNT4
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : CNT4.prj
Compiling included source file '../Fg5-09.v'
Module <CNT4> compiled.
Module <R_SYDFF> compiled.
Continuing compilation of source file 'CNT4.prj'
Compiling included source file 'd:/xilinx_webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'CNT4.prj'
No errors in compilation
Analysis of file <CNT4.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing module <R_SYDFF>.
Module <R_SYDFF> is correct for synthesis.
 
Analyzing top module <CNT4>.
Module <CNT4> is correct for synthesis.

Synthesizing Unit <R_SYDFF>.
    Related source file is ../Fg5-09.v.
    Found 1-bit register for signal <Q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <R_SYDFF> synthesized.


Synthesizing Unit <CNT4>.
    Related source file is ../Fg5-09.v.
Unit <CNT4> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 4
  1-bit register                   : 4

=========================================================================


Starting low level synthesis...

Optimizing unit <R_SYDFF> ...

Optimizing unit <CNT4> ...

Merging netlists...

=========================================================================
Final Results
Output File Name                   : CNT4
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Design Statistics
# Edif Instances                   : 18
# I/Os                             : 6

=========================================================================
CPU : 1.65 / 2.36 s | Elapsed : 1.00 / 1.00 s
 
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