cnt4.mfd
来自「《Verilog-HDL实践与应用系统设计》一书中的光盘源文件」· MFD 代码 · 共 49 行
MFD
49 行
MDF Database: version 1.0
MDF_INFO | CNT4 | XC9536-5-PC44
MACROCELL | 0 | 2 | N18
ATTRIBUTES | 8782642 | 0
INPUTS | 3 | CLK | RSTB | Q<0>".PIN
INPUTP | 3 | 2 | 1 | 5
EQ | 4 |
"Q<0>" := /"Q<0>".PIN
"Q<0>".CLKF = CLK
"Q<0>".RSTF = /RSTB
"Q<0>".PRLD = GND
MACROCELL | 0 | 4 | N19
ATTRIBUTES | 8782642 | 0
INPUTS | 3 | Q<1>".PIN | RSTB | Q<0>".PIN
INPUTP | 3 | 6 | 1 | 5
EQ | 4 |
"Q<1>" := /"Q<1>".PIN
"Q<1>".CLKF = /"Q<0>".PIN
"Q<1>".RSTF = /RSTB
"Q<1>".PRLD = GND
MACROCELL | 0 | 6 | N20
ATTRIBUTES | 8782642 | 0
INPUTS | 3 | Q<2>".PIN | RSTB | Q<1>".PIN
INPUTP | 3 | 7 | 1 | 6
EQ | 4 |
"Q<2>" := /"Q<2>".PIN
"Q<2>".CLKF = /"Q<1>".PIN
"Q<2>".RSTF = /RSTB
"Q<2>".PRLD = GND
MACROCELL | 0 | 5 | N21
ATTRIBUTES | 8782642 | 0
INPUTS | 3 | Q<3>".PIN | RSTB | Q<2>".PIN
INPUTP | 3 | 8 | 1 | 7
EQ | 4 |
"Q<3>" := /"Q<3>".PIN
"Q<3>".CLKF = /"Q<2>".PIN
"Q<3>".RSTF = /RSTB
"Q<3>".PRLD = GND
PIN | RSTB | 1 | 0 | 64 | 4 | 0 | 2 | 0 | 4 | 0 | 6 | 0 | 5
PIN | CLK | 0 | 0 | 64 | 1 | 0 | 2
PIN | Q<0> | 0 | 2 | 64 | 2 | 0 | 2 | 0 | 4
PIN | Q<1> | 0 | 4 | 64 | 2 | 0 | 4 | 0 | 6
PIN | Q<2> | 0 | 6 | 64 | 2 | 0 | 6 | 0 | 5
PIN | Q<3> | 0 | 5 | 64 | 1 | 0 | 5
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