📄 cnt4.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: CNT4 Date: 7-31-2002, 5:18PM
Device Used: XC9536-5-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
4 /36 ( 11%) 12 /180 ( 6%) 4 /36 ( 11%) 6 /34 ( 17%) 6 /72 ( 8%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 2 2 | I/O : 3 25
Output : 0 0 | GCK/IO : 3 0
Bidirectional : 4 4 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 6 6
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 4
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 4 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 4 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
Q<0> 3 3 FB1_3 STD FAST 5 GCK/I/O I/O
Q<1> 3 3 FB1_5 STD FAST 6 GCK/I/O I/O
Q<2> 3 3 FB1_7 STD FAST 7 GCK/I/O I/O
Q<3> 3 3 FB1_6 STD FAST 8 I/O I/O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
CLK FB1_1 2 I/O I
RSTB FB2_1 1 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 4 6 6 12 0/4 17
FB2 0 0 0 0 0/0 17
---- ----- ----- -----
4 12 0/4 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 2 I/O I
(unused) 0 0 0 5 FB1_2 3 I/O
Q<0> 3 0 0 2 FB1_3 STD 5 GCK/I/O I/O
(unused) 0 0 0 5 FB1_4 4 I/O
Q<1> 3 0 0 2 FB1_5 STD 6 GCK/I/O I/O
Q<3> 3 0 0 2 FB1_6 STD 8 I/O I/O
Q<2> 3 0 0 2 FB1_7 STD 7 GCK/I/O I/O
(unused) 0 0 0 5 FB1_8 9 I/O
(unused) 0 0 0 5 FB1_9 11 I/O
(unused) 0 0 0 5 FB1_10 12 I/O
(unused) 0 0 0 5 FB1_11 13 I/O
(unused) 0 0 0 5 FB1_12 14 I/O
(unused) 0 0 0 5 FB1_13 18 I/O
(unused) 0 0 0 5 FB1_14 19 I/O
(unused) 0 0 0 5 FB1_15 20 I/O
(unused) 0 0 0 5 FB1_16 22 I/O
(unused) 0 0 0 5 FB1_17 24 I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: RSTB 3: "Q<0>".PIN 5: "Q<2>".PIN
2: CLK 4: "Q<1>".PIN 6: "Q<3>".PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Q<0> XXX..................................... 3 3
Q<1> X.XX.................................... 3 3
Q<3> X...XX.................................. 3 3
Q<2> X..XX................................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 1 I/O I
(unused) 0 0 0 5 FB2_2 44 I/O
(unused) 0 0 0 5 FB2_3 42 GTS/I/O
(unused) 0 0 0 5 FB2_4 43 I/O
(unused) 0 0 0 5 FB2_5 40 GTS/I/O
(unused) 0 0 0 5 FB2_6 39 GSR/I/O
(unused) 0 0 0 5 FB2_7 38 I/O
(unused) 0 0 0 5 FB2_8 37 I/O
(unused) 0 0 0 5 FB2_9 36 I/O
(unused) 0 0 0 5 FB2_10 35 I/O
(unused) 0 0 0 5 FB2_11 34 I/O
(unused) 0 0 0 5 FB2_12 33 I/O
(unused) 0 0 0 5 FB2_13 29 I/O
(unused) 0 0 0 5 FB2_14 28 I/O
(unused) 0 0 0 5 FB2_15 27 I/O
(unused) 0 0 0 5 FB2_16 26 I/O
(unused) 0 0 0 5 FB2_17 25 I/O
(unused) 0 0 0 5 FB2_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"Q<0>" := /"Q<0>".PIN
"Q<0>".CLKF = CLK
"Q<0>".RSTF = /RSTB
"Q<0>".PRLD = GND
"Q<1>" := /"Q<1>".PIN
"Q<1>".CLKF = /"Q<0>".PIN
"Q<1>".RSTF = /RSTB
"Q<1>".PRLD = GND
"Q<2>" := /"Q<2>".PIN
"Q<2>".CLKF = /"Q<1>".PIN
"Q<2>".RSTF = /RSTB
"Q<2>".PRLD = GND
"Q<3>" := /"Q<3>".PIN
"Q<3>".CLKF = /"Q<2>".PIN
"Q<3>".RSTF = /RSTB
"Q<3>".PRLD = GND
**************************** Device Pin Out ****************************
Device : XC9536-5-PC44
Q Q R
< < T T C S T T T V T
1 0 I I L T I I I C I
> > E E K B E E E C E
--------------------------------
/6 5 4 3 2 1 44 43 42 41 40 \
Q<2> | 7 39 | TIE
Q<3> | 8 38 | TIE
TIE | 9 37 | TIE
GND | 10 36 | TIE
TIE | 11 XC9536-5-PC44 35 | TIE
TIE | 12 34 | TIE
TIE | 13 33 | TIE
TIE | 14 32 | VCC
TDI | 15 31 | GND
TMS | 16 30 | TDO
TCK | 17 29 | TIE
\ 18 19 20 21 22 23 24 25 26 27 28 /
--------------------------------
T T T V T G T T T T T
I I I C I N I I I I I
E E E C E D E E E E E
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9536-5-PC44
Use Timing Constraints : ON
Use Design Location Constraints : ON
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 36
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