cnt4.gyd

《Verilog-HDL实践与应用系统设计》一书中的光盘源文件

Pin Freeze File:  version E.33

953644PC XC9536-5-PC44
RSTB S:PIN1
CLK S:PIN2
Q<0> S:PIN5
Q<1> S:PIN6
Q<2> S:PIN7
Q<3> S:PIN8


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_3 N18
PARTITION FB1_5 N19 N21 N20