ch_counter.gyd

《Verilog-HDL实践与应用系统设计》一书中的光盘源文件

Pin Freeze File:  version E.33

957244 XC9572-7-PC44
CLK S:PIN7
START S:PIN5
RB1 S:PIN1
DA_OUT<0> S:PIN44
DA_OUT<10> S:PIN29
DA_OUT<11> S:PIN28
DA_OUT<12> S:PIN27
DA_OUT<13> S:PIN26
DA_OUT<14> S:PIN25
DA_OUT<15> S:PIN24
DA_OUT<16> S:PIN22
DA_OUT<17> S:PIN20
DA_OUT<18> S:PIN19
DA_OUT<19> S:PIN18
DA_OUT<1> S:PIN43
DA_OUT<20> S:PIN14
DA_OUT<21> S:PIN13
DA_OUT<22> S:PIN12
DA_OUT<23> S:PIN11
DA_OUT<2> S:PIN38
DA_OUT<3> S:PIN37
DA_OUT<4> S:PIN36
DA_OUT<5> S:PIN35
DA_OUT<6> S:PIN40
DA_OUT<7> S:PIN42
DA_OUT<8> S:PIN34
DA_OUT<9> S:PIN33


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.


PARTITION FB2_2 N77
PARTITION FB2_5 N76 N75
PARTITION FB2_8 N74
PARTITION FB2_11 N78
PARTITION FB2_14 N79 N69
PARTITION FB2_17 N58

PARTITION FB3_2 N73
PARTITION FB3_5 N72
PARTITION FB3_8 N71 N70
PARTITION FB3_11 N68 "CNT100/Q_4" "CNT100/Q_3" N67
		 N66 "CNT100/Q_1" N65 "CNT100/Q_0"
		
PARTITION FB4_2 N64
PARTITION FB4_5 N63
PARTITION FB4_8 N62 N61
PARTITION FB4_11 N60
PARTITION FB4_13 "CNT100/Q_6" N59 N81 "CNT100/Q_5"
		 N80 "CNT100/Q_2"