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📄 ch_counter.rpt

📁 《Verilog-HDL实践与应用系统设计》一书中的光盘源文件
💻 RPT
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                       12: "DA_OUT<15>".PIN  22: CLK 
  2: "CNT100/Q_1.FBK".LFBK 
                       13: "DA_OUT<1>".PIN   23: START 
  3: "CNT100/Q_2"      14: "DA_OUT<2>".PIN   24: N65.FBK.LFBK 
  4: "CNT100/Q_3.FBK".LFBK 
                       15: "DA_OUT<3>".PIN   25: N66.FBK.LFBK 
  5: "CNT100/Q_6"      16: "DA_OUT<4>".PIN   26: N67.FBK.LFBK 
  6: "DA_OUT<0>".PIN   17: "DA_OUT<5>".PIN   27: N68.FBK.LFBK 
  7: "DA_OUT<10>".PIN  18: "DA_OUT<6>".PIN   28: N70.FBK.LFBK 
  8: "DA_OUT<11>".PIN  19: "DA_OUT<7>".PIN   29: N71.FBK.LFBK 
  9: "DA_OUT<12>".PIN  20: "DA_OUT<8>".PIN   30: N72.FBK.LFBK 
 10: "DA_OUT<13>".PIN  21: "DA_OUT<9>".PIN   31: RB1 
 11: "DA_OUT<14>".PIN 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
DA_OUT<23>           ....XXXXXXXXXXXXXXXXX..XXXXXXXX......... 25      25
DA_OUT<22>           ....XXXXXXXXXXXXXXXXX..XXXXXX.X......... 24      24
DA_OUT<21>           ....XXXXXXXXXXXXXXXXX..XXXXX..X......... 23      23
DA_OUT<20>           ....XXXXXXXXXXXXXXXXX..XXXX...X......... 22      22
DA_OUT<19>           ....XXXXXXXXXXXXXXXXX..XXX....X......... 21      21
CNT100/Q_4           XXXX.................XX.......X......... 7       7
CNT100/Q_3           XXX..................XX.......X......... 6       6
DA_OUT<18>           ....XXXXXXXXXXXXXXXXX..XX.....X......... 20      20
DA_OUT<17>           ....XXXXXXXXXXXXXXXXX..X......X......... 19      19
CNT100/Q_1           X....................XX.......X......... 4       4
DA_OUT<16>           ....XXXXXXXXXXXXXXXXX.........X......... 18      18
CNT100/Q_0           X....................XX.......X......... 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               25/11
Number of signals used by logic mapping into function block:  25
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB4_1               (b)     
DA_OUT<15>            3       0     0   2     FB4_2   STD   24    I/O     I/O
(unused)              0       0     0   5     FB4_3               (b)     
(unused)              0       0     0   5     FB4_4               (b)     
DA_OUT<14>            3       0     0   2     FB4_5   STD   25    I/O     I/O
(unused)              0       0     0   5     FB4_6               (b)     
(unused)              0       0     0   5     FB4_7               (b)     
DA_OUT<13>            3       0     0   2     FB4_8   STD   26    I/O     I/O
DA_OUT<12>            3       0     0   2     FB4_9   STD   27    I/O     I/O
(unused)              0       0     0   5     FB4_10              (b)     
DA_OUT<11>            3       0     0   2     FB4_11  STD   28    I/O     I/O
(unused)              0       0     0   5     FB4_12              (b)     
CNT100/Q_6            4       0     0   1     FB4_13  STD         (b)     (b)
DA_OUT<10>            3       0     0   2     FB4_14  STD   29    I/O     I/O
DA_OUT<9>             3       0     0   2     FB4_15  STD   33    I/O     I/O
CNT100/Q_5            4       0     0   1     FB4_16  STD         (b)     (b)
DA_OUT<8>             3       0     0   2     FB4_17  STD   34    I/O     I/O
CNT100/Q_2            5       0     0   0     FB4_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: "CNT100/Q_0"      10: "DA_OUT<2>".PIN   18: N59.FBK.LFBK 
  2: "CNT100/Q_1"      11: "DA_OUT<3>".PIN   19: N60.FBK.LFBK 
  3: "CNT100/Q_2.FBK".LFBK 
                       12: "DA_OUT<4>".PIN   20: N61.FBK.LFBK 
  4: "CNT100/Q_3"      13: "DA_OUT<5>".PIN   21: N62.FBK.LFBK 
  5: "CNT100/Q_4"      14: "DA_OUT<6>".PIN   22: N63.FBK.LFBK 
  6: "CNT100/Q_5.FBK".LFBK 
                       15: "DA_OUT<7>".PIN   23: N80.FBK.LFBK 
  7: "CNT100/Q_6.FBK".LFBK 
                       16: CLK               24: N81.FBK.LFBK 
  8: "DA_OUT<0>".PIN   17: START             25: RB1 
  9: "DA_OUT<1>".PIN  

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
DA_OUT<15>           ......XXXXXXXXX..XXXXXXXX............... 17      17
DA_OUT<14>           ......XXXXXXXXX..XXXX.XXX............... 16      16
DA_OUT<13>           ......XXXXXXXXX..XXX..XXX............... 15      15
DA_OUT<12>           ......XXXXXXXXX..XX...XXX............... 14      14
DA_OUT<11>           ......XXXXXXXXX..X....XXX............... 13      13
CNT100/Q_6           XXXXXXX........XX.......X............... 10      10
DA_OUT<10>           ......XXXXXXXXX.......XXX............... 12      12
DA_OUT<9>            ......XXXXXXXXX.......X.X............... 11      11
CNT100/Q_5           XXXXXXX........XX.......X............... 10      10
DA_OUT<8>            ......XXXXXXXXX.........X............... 10      10
CNT100/Q_2           XXXXXXX........XX.......X............... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

 "CNT100/Q_0"  :=  /"CNT100/Q_0.FBK".LFBK
    "CNT100/Q_0".CLKF  =  CLK * START
    "CNT100/Q_0".RSTF  =  /RB1
    "CNT100/Q_0".PRLD  =  GND    

 "CNT100/Q_1".T  =  "CNT100/Q_0.FBK".LFBK
    "CNT100/Q_1".CLKF  =  CLK * START
    "CNT100/Q_1".RSTF  =  /RB1
    "CNT100/Q_1".PRLD  =  GND    

/"CNT100/Q_2".T  =  /"CNT100/Q_0"
	+ /"CNT100/Q_1"
	+ /"CNT100/Q_3" * /"CNT100/Q_4" * 
	/"CNT100/Q_2.FBK".LFBK * "CNT100/Q_5.FBK".LFBK * "CNT100/Q_6.FBK".LFBK
    "CNT100/Q_2".CLKF  =  CLK * START
    "CNT100/Q_2".RSTF  =  /RB1
    "CNT100/Q_2".PRLD  =  GND    

 "CNT100/Q_3".T  =  "CNT100/Q_2" * "CNT100/Q_0.FBK".LFBK * 
	"CNT100/Q_1.FBK".LFBK
    "CNT100/Q_3".CLKF  =  CLK * START
    "CNT100/Q_3".RSTF  =  /RB1
    "CNT100/Q_3".PRLD  =  GND    

 "CNT100/Q_4".T  =  "CNT100/Q_2" * "CNT100/Q_0.FBK".LFBK * 
	"CNT100/Q_1.FBK".LFBK * "CNT100/Q_3.FBK".LFBK
    "CNT100/Q_4".CLKF  =  CLK * START
    "CNT100/Q_4".RSTF  =  /RB1
    "CNT100/Q_4".PRLD  =  GND    

 "CNT100/Q_5".T  =  "CNT100/Q_0" * "CNT100/Q_1" * "CNT100/Q_3" * 
	"CNT100/Q_4" * "CNT100/Q_2.FBK".LFBK
	+ "CNT100/Q_0" * "CNT100/Q_1" * /"CNT100/Q_3" * 
	/"CNT100/Q_4" * /"CNT100/Q_2.FBK".LFBK * "CNT100/Q_5.FBK".LFBK * 
	"CNT100/Q_6.FBK".LFBK
    "CNT100/Q_5".CLKF  =  CLK * START
    "CNT100/Q_5".RSTF  =  /RB1
    "CNT100/Q_5".PRLD  =  GND    

 "CNT100/Q_6".T  =  "CNT100/Q_0" * "CNT100/Q_1" * "CNT100/Q_3" * 
	"CNT100/Q_4" * "CNT100/Q_2.FBK".LFBK * "CNT100/Q_5.FBK".LFBK
	+ "CNT100/Q_0" * "CNT100/Q_1" * /"CNT100/Q_3" * 
	/"CNT100/Q_4" * /"CNT100/Q_2.FBK".LFBK * "CNT100/Q_5.FBK".LFBK * 
	"CNT100/Q_6.FBK".LFBK
    "CNT100/Q_6".CLKF  =  CLK * START
    "CNT100/Q_6".RSTF  =  /RB1
    "CNT100/Q_6".PRLD  =  GND    

 "DA_OUT<0>"  :=  /N58.FBK.LFBK
    "DA_OUT<0>".CLKF  =  /"CNT100/Q_6"
    "DA_OUT<0>".SETF  =  /RB1
    "DA_OUT<0>".PRLD  =  VCC    

 "DA_OUT<10>".T  =  /N80.FBK.LFBK * /N81.FBK.LFBK * /"DA_OUT<0>".PIN * 
	/"DA_OUT<1>".PIN * /"DA_OUT<2>".PIN * /"DA_OUT<3>".PIN * 
	/"DA_OUT<4>".PIN * /"DA_OUT<5>".PIN * /"DA_OUT<6>".PIN * 
	/"DA_OUT<7>".PIN
    "DA_OUT<10>".CLKF  =  /"CNT100/Q_6.FBK".LFBK
    "DA_OUT<10>".SETF  =  /RB1
    "DA_OUT<10>".PRLD  =  VCC    

 "DA_OUT<11>".T  =  /N80.FBK.LFBK * /N81.FBK.LFBK * /N59.FBK.LFBK * 
	/"DA_OUT<0>".PIN * /"DA_OUT<1>".PIN * /"DA_OUT<2>".PIN * 
	/"DA_OUT<3>".PIN * /"DA_OUT<4>".PIN * /"DA_OUT<5>".PIN * 
	/"DA_OUT<6>".PIN * /"DA_OUT<7>".PIN
    "DA_OUT<11>".CLKF  =  /"CNT100/Q_6.FBK".LFBK
    "DA_OUT<11>".SETF  =  /RB1
    "DA_OUT<11>".PRLD  =  VCC    

 "DA_OUT<12>".T  =  /N80.FBK.LFBK * /N81.FBK.LFBK * /N59.FBK.LFBK * 
	/N60.FBK.LFBK * /"DA_OUT<0>".PIN * /"DA_OUT<1>".PIN * 
	/"DA_OUT<2>".PIN * /"DA_OUT<3>".PIN * /"DA_OUT<4>".PIN * 
	/"DA_OUT<5>".PIN * /"DA_OUT<6>".PIN * /"DA_OUT<7>".PIN
    "DA_OUT<12>".CLKF  =  /"CNT100/Q_6.FBK".LFBK
    "DA_OUT<12>".SETF  =  /RB1
    "DA_OUT<12>".PRLD  =  VCC    

 "DA_OUT<13>".T  =  /N80.FBK.LFBK * /N81.FBK.LFBK * /N59.FBK.LFBK * 
	/N60.FBK.LFBK * /N61.FBK.LFBK * /"DA_OUT<0>".PIN * /"DA_OUT<1>".PIN * 
	/"DA_OUT<2>".PIN * /"DA_OUT<3>".PIN * /"DA_OUT<4>".PIN * 
	/"DA_OUT<5>".PIN * /"DA_OUT<6>".PIN * /"DA_OUT<7>".PIN
    "DA_OUT<13>".CLKF  =  /"CNT100/Q_6.FBK".LFBK
    "DA_OUT<13>".SETF  =  /RB1
    "DA_OUT<13>".PRLD  =  VCC    

 "DA_OUT<14>".T  =  /N80.FBK.LFBK * /N81.FBK.LFBK * /N59.FBK.LFBK * 
	/N60.FBK.LFBK * /N61.FBK.LFBK * /N62.FBK.LFBK * /"DA_OUT<0>".PIN * 
	/"DA_OUT<1>".PIN * /"DA_OUT<2>".PIN * /"DA_OUT<3>".PIN * 
	/"DA_OUT<4>".PIN * /"DA_OUT<5>".PIN * /"DA_OUT<6>".PIN * 
	/"DA_OUT<7>".PIN
    "DA_OUT<14>".CLKF  =  /"CNT100/Q_6.FBK".LFBK
    "DA_OUT<14>".SETF  =  /RB1
    "DA_OUT<14>".PRLD  =  VCC    

 "DA_OUT<15>".T  =  /N80.FBK.LFBK * /N81.FBK.LFBK * /N59.FBK.LFBK * 
	/N60.FBK.LFBK * /N61.FBK.LFBK * /N62.FBK.LFBK * /N63.FBK.LFBK * 
	/"DA_OUT<0>".PIN * /"DA_OUT<1>".PIN * /"DA_OUT<2>".PIN * 
	/"DA_OUT<3>".PIN * /"DA_OUT<4>".PIN * /"DA_OUT<5>".PIN * 
	/"DA_OUT<6>".PIN * /"DA_OUT<7>".PIN
    "DA_OUT<15>".CLKF  =  /"CNT100/Q_6.FBK".LFBK
    "DA_OUT<15>".SETF  =  /RB1
    "DA_OUT<15>".PRLD  =  VCC    

 "DA_OUT<16>".T  =  /"DA_OUT<0>".PIN * /"DA_OUT<10>".PIN * 

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