📄 ch_counter.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: CH_COUNTER Date: 8-10-2002, 5:29PM
Device Used: XC9572-7-PC44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
31 /72 ( 43%) 97 /360 ( 26%) 31 /72 ( 43%) 27 /34 ( 79%) 65 /144 ( 45%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 3 3 | I/O : 23 5
Output : 8 8 | GCK/IO : 2 1
Bidirectional : 16 16 | GTS/IO : 2 0
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 27 27
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 31
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 31 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 31 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
CNT100/Q_0 3 4 FB3_18 STD (b) (b)
CNT100/Q_1 3 4 FB3_16 STD (b) (b)
CNT100/Q_2 5 10 FB4_18 STD (b) (b)
CNT100/Q_3 3 6 FB3_13 STD (b) (b)
CNT100/Q_4 3 7 FB3_12 STD (b) (b)
CNT100/Q_5 4 10 FB4_16 STD (b) (b)
CNT100/Q_6 4 10 FB4_13 STD (b) (b)
DA_OUT<0> 3 3 FB2_17 STD FAST 44 I/O I/O
DA_OUT<10> 3 12 FB4_14 STD FAST 29 I/O I/O
DA_OUT<11> 3 13 FB4_11 STD FAST 28 I/O I/O
DA_OUT<12> 3 14 FB4_9 STD FAST 27 I/O I/O
DA_OUT<13> 3 15 FB4_8 STD FAST 26 I/O I/O
DA_OUT<14> 3 16 FB4_5 STD FAST 25 I/O I/O
DA_OUT<15> 3 17 FB4_2 STD FAST 24 I/O I/O
DA_OUT<16> 3 18 FB3_17 STD FAST 22 I/O O
DA_OUT<17> 3 19 FB3_15 STD FAST 20 I/O O
DA_OUT<18> 3 20 FB3_14 STD FAST 19 I/O O
DA_OUT<19> 3 21 FB3_11 STD FAST 18 I/O O
DA_OUT<1> 3 3 FB2_15 STD FAST 43 I/O I/O
DA_OUT<20> 3 22 FB3_9 STD FAST 14 I/O O
DA_OUT<21> 3 23 FB3_8 STD FAST 13 I/O O
DA_OUT<22> 3 24 FB3_5 STD FAST 12 I/O O
DA_OUT<23> 3 25 FB3_2 STD FAST 11 I/O O
DA_OUT<2> 3 4 FB2_8 STD FAST 38 I/O I/O
DA_OUT<3> 3 5 FB2_6 STD FAST 37 I/O I/O
DA_OUT<4> 3 6 FB2_5 STD FAST 36 I/O I/O
DA_OUT<5> 3 7 FB2_2 STD FAST 35 I/O I/O
DA_OUT<6> 3 8 FB2_11 STD FAST 40 GTS/I/O I/O
DA_OUT<7> 3 9 FB2_14 STD FAST 42 GTS/I/O I/O
DA_OUT<8> 3 10 FB4_17 STD FAST 34 I/O I/O
DA_OUT<9> 3 11 FB4_15 STD FAST 33 I/O I/O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
CLK FB1_14 7 GCK/I/O I
RB1 FB1_2 1 I/O I
START FB1_9 5 GCK/I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 0 0 0 0 0/0 9
FB2 8 9 9 24 0/8 9
FB3 12 31 31 36 8/0 8
FB4 11 25 25 37 0/8 8
---- ----- ----- -----
31 97 8/16 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O I
(unused) 0 0 0 5 FB1_3 (b)
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 2 I/O
(unused) 0 0 0 5 FB1_6 3 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 4 I/O
(unused) 0 0 0 5 FB1_9 5 GCK/I/O I
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 6 GCK/I/O
(unused) 0 0 0 5 FB1_12 (b)
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 7 GCK/I/O I
(unused) 0 0 0 5 FB1_15 8 I/O
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 9 I/O
(unused) 0 0 0 5 FB1_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 9/27
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
DA_OUT<5> 3 0 0 2 FB2_2 STD 35 I/O I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
DA_OUT<4> 3 0 0 2 FB2_5 STD 36 I/O I/O
DA_OUT<3> 3 0 0 2 FB2_6 STD 37 I/O I/O
(unused) 0 0 0 5 FB2_7 (b)
DA_OUT<2> 3 0 0 2 FB2_8 STD 38 I/O I/O
(unused) 0 0 0 5 FB2_9 39 GSR/I/O
(unused) 0 0 0 5 FB2_10 (b)
DA_OUT<6> 3 0 0 2 FB2_11 STD 40 GTS/I/O I/O
(unused) 0 0 0 5 FB2_12 (b)
(unused) 0 0 0 5 FB2_13 (b)
DA_OUT<7> 3 0 0 2 FB2_14 STD 42 GTS/I/O I/O
DA_OUT<1> 3 0 0 2 FB2_15 STD 43 I/O I/O
(unused) 0 0 0 5 FB2_16 (b)
DA_OUT<0> 3 0 0 2 FB2_17 STD 44 I/O I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: "CNT100/Q_6" 4: N74.FBK.LFBK 7: N77.FBK.LFBK
2: N58.FBK.LFBK 5: N75.FBK.LFBK 8: N78.FBK.LFBK
3: N69.FBK.LFBK 6: N76.FBK.LFBK 9: RB1
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DA_OUT<5> XXXXXX..X............................... 7 7
DA_OUT<4> XXXXX...X............................... 6 6
DA_OUT<3> XXXX....X............................... 5 5
DA_OUT<2> XXX.....X............................... 4 4
DA_OUT<6> XXXXXXX.X............................... 8 8
DA_OUT<7> XXXXXXXXX............................... 9 9
DA_OUT<1> XX......X............................... 3 3
DA_OUT<0> XX......X............................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 31/5
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
DA_OUT<23> 3 0 0 2 FB3_2 STD 11 I/O O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
DA_OUT<22> 3 0 0 2 FB3_5 STD 12 I/O O
(unused) 0 0 0 5 FB3_6 (b)
(unused) 0 0 0 5 FB3_7 (b)
DA_OUT<21> 3 0 0 2 FB3_8 STD 13 I/O O
DA_OUT<20> 3 0 0 2 FB3_9 STD 14 I/O O
(unused) 0 0 0 5 FB3_10 (b)
DA_OUT<19> 3 0 0 2 FB3_11 STD 18 I/O O
CNT100/Q_4 3 0 0 2 FB3_12 STD (b) (b)
CNT100/Q_3 3 0 0 2 FB3_13 STD (b) (b)
DA_OUT<18> 3 0 0 2 FB3_14 STD 19 I/O O
DA_OUT<17> 3 0 0 2 FB3_15 STD 20 I/O O
CNT100/Q_1 3 0 0 2 FB3_16 STD (b) (b)
DA_OUT<16> 3 0 0 2 FB3_17 STD 22 I/O O
CNT100/Q_0 3 0 0 2 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "CNT100/Q_0.FBK".LFBK
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