📄 test_bench_top.v.bak
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//$display("pixel=%0d, line=%0d, (%0t)",p,l,$time);
if(bank[0]) vbase = vbarb[31:2];
else vbase = vbara[31:2];
if(bank[0]) cbase = 32'h0000_0c00;
else cbase = 32'h0000_0800;
// Depending on Mode, determine pixel data
// pixel number = line * (thgate + 1) + p
pn = l * (thgate + 1) + p;
case(mode)
0: // 24 bit/pixel mode
begin
pra = pn[31:2] * 3; // Pixel relative Address
paa = pra + vbase; // Pixel Absolute Address
// Pixel Data
case(pn[1:0])
0:
begin
tmp = s0.mem[paa];
pd = tmp[31:8];
end
1:
begin
tmp = s0.mem[paa];
pd[23:16] = tmp[7:0];
tmp = s0.mem[paa+1];
pd[15:0] = tmp[31:16];
end
2:
begin
tmp = s0.mem[paa+1];
pd[23:8] = tmp[15:0];
tmp = s0.mem[paa+2];
pd[7:0] = tmp[31:24];
end
3:
begin
tmp = s0.mem[paa+2];
pd = tmp[23:0];
end
endcase
end
1: // 8 bit/pixel grayscale mode
begin
pra = pn[31:2]; // Pixel relative Address
paa = pra + vbase; // Pixel Absolute Address
case(pn[1:0])
0:
begin
tmp = s0.mem[paa];
pd = { tmp[31:24], tmp[31:24], tmp[31:24] };
end
1:
begin
tmp = s0.mem[paa];
pd = { tmp[23:16], tmp[23:16], tmp[23:16] };
end
2:
begin
tmp = s0.mem[paa];
pd = { tmp[15:8], tmp[15:8], tmp[15:8] };
end
3:
begin
tmp = s0.mem[paa];
pd = { tmp[7:0], tmp[7:0], tmp[7:0] };
end
endcase
end
2: // 8 bit/pixel Pseudo Color mode
begin
pra = pn[31:2]; // Pixel relative Address
paa = pra + vbase; // Pixel Absolute Address
case(pn[1:0])
0:
begin
tmp = s0.mem[paa];
tmp = s0.mem[cbase[31:2] + tmp[31:24]];
pd = tmp[23:0];
end
1:
begin
tmp = s0.mem[paa];
tmp = s0.mem[cbase[31:2] + tmp[23:16]];
pd = tmp[23:0];
end
2:
begin
tmp = s0.mem[paa];
tmp = s0.mem[cbase[31:2] + tmp[15:8]];
pd = tmp[23:0];
end
3:
begin
tmp = s0.mem[paa];
tmp = s0.mem[cbase[31:2] + tmp[7:0]];
pd = tmp[23:0];
end
endcase
end
3: // 16 bit/pixel mode
begin
pra = pn[31:1]; // Pixel relative Address
paa = pra + vbase; // Pixel Absolute Address
case(pn[0])
0:
begin
tmp = s0.mem[paa];
tmp[15:0] = tmp[31:16];
pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
end
1:
begin
tmp = s0.mem[paa];
pd = {tmp[15:11], 3'h0, tmp[10:5], 2'h0, tmp[4:0], 3'h0};
end
endcase
end
endcase
if(pd !== {red, green, blue} )
begin
$display("ERROR: Pixel Data Mismatch: Expected: %h, Got: %h %h %h",
pd, red, green, blue);
$display(" pixel=%0d, line=%0d, (%0t)",p,l,$time);
error_cnt = error_cnt + 1;
end
@(posedge pclk);
end
end
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
end
repeat(10) @(posedge clk);
$finish;
end
/////////////////////////////////////////////////////////////////////
//
// Sync Monitor
//
`ifdef VGA_12BIT_DVI
sync_check #(PCLK_C*2) ucheck(
`else
sync_check #(PCLK_C) ucheck(
`endif
.pclk( pclk ),
.rst( rst ),
.enable( scen ),
.hsync( hsync ),
.vsync( vsync ),
.csync( csync ),
.blanc( blanc ),
.hpol( hpol ),
.vpol( vpol ),
.cpol( cpol ),
.bpol( bpol ),
.thsync( thsync ),
.thgdel( thgdel ),
.thgate( thgate ),
.thlen( thlen ),
.tvsync( tvsync ),
.tvgdel( tvgdel ),
.tvgate( tvgate ),
.tvlen( tvlen ) );
/////////////////////////////////////////////////////////////////////
//
// Video Data Monitor
//
/////////////////////////////////////////////////////////////////////
//
// WISHBONE revB.3 checker
//
wb_b3_check u_wb_check (
.clk_i ( clk ),
.cyc_i ( wb_cyc_o ),
.stb_i ( wb_stb_o ),
.cti_i ( wb_cti_o ),
.bte_i ( wb_bte_o ),
.we_i ( wb_we_o ),
.ack_i ( wb_ack_i ),
.err_i ( wb_err_i ),
.rty_i ( 1'b0 ) );
/////////////////////////////////////////////////////////////////////
//
// Watchdog Counter
//
always @(posedge clk)
if(wb_cyc_i | wb_cyc_o | wb_ack_i | wb_ack_o | hsync)
wd_cnt <= #1 0;
else
wd_cnt <= #1 wd_cnt + 1;
always @(wd_cnt)
if(wd_cnt>9000)
begin
$display("\n\n*************************************\n");
$display("ERROR: Watch Dog Counter Expired\n");
$display("*************************************\n\n\n");
$finish;
end
always @(posedge int)
if(int_warn)
begin
$display("\n\n*************************************\n");
$display("WARNING: Recieved Interrupt (%0t)", $time);
$display("*************************************\n\n\n");
end
always #2.5 clk = ~clk;
always #(PCLK_C/2) pclk_i = ~pclk_i;
/////////////////////////////////////////////////////////////////////
//
// WISHBONE VGA/LCD IP Core
//
// Module Prototype
vga_enh_top #(1'b0, LINE_FIFO_AWIDTH) u0 (
.wb_clk_i ( clk ),
.wb_rst_i ( 1'b0 ),
.rst_i ( rst ),
.wb_inta_o ( int ),
//-- slave signals
.wbs_adr_i ( wb_addr_i[11:0] ),
.wbs_dat_i ( wb_data_i ),
.wbs_dat_o ( wb_data_o ),
.wbs_sel_i ( wb_sel_i ),
.wbs_we_i ( wb_we_i ),
.wbs_stb_i ( wb_stb_i ),
.wbs_cyc_i ( wb_cyc_i ),
.wbs_ack_o ( wb_ack_o ),
.wbs_rty_o ( wb_rty_o ),
.wbs_err_o ( wb_err_o ),
//-- master signals
.wbm_adr_o ( wb_addr_o[31:0] ),
.wbm_dat_i ( wbm_data_i ),
.wbm_sel_o ( wb_sel_o ),
.wbm_we_o ( wb_we_o ),
.wbm_stb_o ( wb_stb_o ),
.wbm_cyc_o ( wb_cyc_o ),
.wbm_cti_o ( wb_cti_o ),
.wbm_bte_o ( wb_bte_o ),
.wbm_ack_i ( wb_ack_i ),
.wbm_err_i ( wb_err_i ),
//-- VGA signals
.clk_p_i ( pclk_i ),
`ifdef VGA_12BIT_DVI
.dvi_pclk_p_o ( dvi_pclk_p_o ),
.dvi_pclk_m_o ( dvi_pclk_m_o ),
.dvi_hsync_o ( dvi_hsync_o ),
.dvi_vsync_o ( dvi_vsync_o ),
.dvi_de_o ( dvi_de_o ),
.dvi_d_o ( dvi_d_o ),
`endif
.clk_p_o ( pclk ),
.hsync_pad_o ( hsync ),
.vsync_pad_o ( vsync ),
.csync_pad_o ( csync ),
.blank_pad_o ( blanc ),
.r_pad_o ( red ),
.g_pad_o ( green ),
.b_pad_o ( blue )
);
wb_mast m0( .clk( clk ),
.rst( rst ),
.adr( wb_addr_i ),
.din( wb_data_o ),
.dout( wb_data_i ),
.cyc( wb_cyc_i ),
.stb( wb_stb_i ),
.sel( wb_sel_i ),
.we( wb_we_i ),
.ack( wb_ack_o ),
.err( wb_err_o ),
.rty( 1'b0 )
);
wb_slv #(24) s0(.clk( clk ),
.rst( rst ),
.adr( {1'b0, wb_addr_o[30:0]} ),
.din( 32'h0 ),
.dout( wbm_data_i ),
.cyc( wb_cyc_o ),
.stb( wb_stb_o ),
.sel( wb_sel_o ),
.we( wb_we_o ),
.ack( wb_ack_i ),
.err( wb_err_i ),
.rty( )
);
`include "tests.v"
endmodule
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