zongtu.rpt

用verilog语言写的拔河游戏机

-- Equation name is 'adr1', type is output 
adr1     =  _LC3_B3;

-- Node name is 'adr2' 
-- Equation name is 'adr2', type is output 
adr2     =  _LC8_B3;

-- Node name is 'adr3' 
-- Equation name is 'adr3', type is output 
adr3     =  _LC2_B3;

-- Node name is 'adr4' 
-- Equation name is 'adr4', type is output 
adr4     =  _LC7_B3;

-- Node name is 'adr5' 
-- Equation name is 'adr5', type is output 
adr5     =  _LC4_C24;

-- Node name is 'adr6' 
-- Equation name is 'adr6', type is output 
adr6     =  _LC1_B3;

-- Node name is 'adr7' 
-- Equation name is 'adr7', type is output 
adr7     =  _LC6_B3;

-- Node name is 'cn4' 
-- Equation name is 'cn4', type is output 
cn4      =  _LC6_B17;

-- Node name is 'dout0' 
-- Equation name is 'dout0', type is bidir 
dout0    = TRI(_LC1_B10,  _LC4_B8);

-- Node name is 'dout1' 
-- Equation name is 'dout1', type is bidir 
dout1    = TRI(_LC5_B19,  _LC4_B8);

-- Node name is 'dout2' 
-- Equation name is 'dout2', type is bidir 
dout2    = TRI(_LC6_B8,  _LC4_B8);

-- Node name is 'dout3' 
-- Equation name is 'dout3', type is bidir 
dout3    = TRI(_LC1_B5,  _LC4_B8);

-- Node name is 'dout4' 
-- Equation name is 'dout4', type is bidir 
dout4    = TRI(_LC1_B16,  _LC4_B8);

-- Node name is 'dout5' 
-- Equation name is 'dout5', type is bidir 
dout5    = TRI(_LC8_B24,  _LC4_B8);

-- Node name is 'dout6' 
-- Equation name is 'dout6', type is bidir 
dout6    = TRI(_LC2_B4,  _LC4_B8);

-- Node name is 'dout7' 
-- Equation name is 'dout7', type is bidir 
dout7    = TRI(_LC8_B14,  _LC4_B8);

-- Node name is 'indata_a' 
-- Equation name is 'indata_a', type is output 
indata_a =  _LC7_A1;

-- Node name is 'indata_b' 
-- Equation name is 'indata_b', type is output 
indata_b =  _LC1_A2;

-- Node name is 'indata_c' 
-- Equation name is 'indata_c', type is output 
indata_c =  _LC4_A1;

-- Node name is 'indata_d' 
-- Equation name is 'indata_d', type is output 
indata_d =  _LC5_A11;

-- Node name is 'indata-f' 
-- Equation name is 'indata-f', type is output 
indata-f =  _LC8_A1;

-- Node name is 'indata_g' 
-- Equation name is 'indata_g', type is output 
indata_g =  _LC3_A1;

-- Node name is 'indata_gw' 
-- Equation name is 'indata_gw', type is output 
indata_gw = !_LC7_C21;

-- Node name is 'indata_gw~1' 
-- Equation name is 'indata_gw~1', location is LC7_C21, type is buried.
-- synthesized logic cell 
_LC7_C21 = LCELL( scan_clk);

-- Node name is 'indata_sw' 
-- Equation name is 'indata_sw', type is output 
indata_sw =  _LC2_C16;

-- Node name is 'indata_sw~1' 
-- Equation name is 'indata_sw~1', location is LC2_C16, type is buried.
-- synthesized logic cell 
_LC2_C16 = LCELL( scan_clk);

-- Node name is 'ndata_e' 
-- Equation name is 'ndata_e', type is output 
ndata_e  =  _LC8_A2;

-- Node name is 's0' 
-- Equation name is 's0', type is output 
s0       =  _LC1_B22;

-- Node name is 's1' 
-- Equation name is 's1', type is output 
s1       =  _LC6_B22;

-- Node name is 's2' 
-- Equation name is 's2', type is output 
s2       =  _LC2_B22;

-- Node name is 's3' 
-- Equation name is 's3', type is output 
s3       =  _LC5_B22;

-- Node name is '|alu8:47|BCD_7SEG:81|~492~1' 
-- Equation name is '_LC1_A11', type is buried 
-- synthesized logic cell 
!_LC1_A11 = _LC1_A11~NOT;
_LC1_A11~NOT = LCELL( _EQ001);
  _EQ001 = !_LC1_B1 & !_LC1_B11;

-- Node name is '|alu8:47|BCD_7SEG:81|:516' 
-- Equation name is '_LC3_A2', type is buried 
_LC3_A2  = LCELL( _EQ002);
  _EQ002 = !_LC1_B1 &  _LC1_B11 & !_LC3_B1 & !_LC4_B1;

-- Node name is '|alu8:47|BCD_7SEG:81|:528' 
-- Equation name is '_LC2_A2', type is buried 
!_LC2_A2 = _LC2_A2~NOT;
_LC2_A2~NOT = LCELL( _EQ003);
  _EQ003 =  _LC1_B11
         # !_LC1_B1
         #  _LC3_B1
         #  _LC4_B1;

-- Node name is '|alu8:47|BCD_7SEG:81|:545' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ004);
  _EQ004 =  _LC4_B1
         #  _LC1_B11 & !_LC3_B1
         # !_LC1_B1 &  _LC1_B11
         # !_LC1_B11 &  _LC3_B1
         # !_LC1_B1 &  _LC3_B1;

-- Node name is '|alu8:47|BCD_7SEG:81|~579~1' 
-- Equation name is '_LC5_A1', type is buried 
-- synthesized logic cell 
!_LC5_A1 = _LC5_A1~NOT;
_LC5_A1~NOT = LCELL( _EQ005);
  _EQ005 = !_LC3_B1
         #  _LC4_B1
         # !_LC1_B1 & !_LC1_B11
         #  _LC1_B1 &  _LC1_B11;

-- Node name is '|alu8:47|BCD_7SEG:81|:591' 
-- Equation name is '_LC8_A1', type is buried 
_LC8_A1  = LCELL( _EQ006);
  _EQ006 =  _LC1_B11 &  _LC4_B1
         # !_LC1_B1 &  _LC1_B11 &  _LC3_B1
         # !_LC1_B11 &  _LC3_B1 & !_LC4_B1
         # !_LC1_B1 &  _LC3_B1 & !_LC4_B1
         # !_LC3_B1 &  _LC4_B1
         # !_LC1_B1 & !_LC1_B11 & !_LC3_B1
         # !_LC1_B1 & !_LC1_B11 & !_LC4_B1;

-- Node name is '|alu8:47|BCD_7SEG:81|~635~1' 
-- Equation name is '_LC4_A2', type is buried 
-- synthesized logic cell 
_LC4_A2  = LCELL( _EQ007);
  _EQ007 = !_LC1_B1
         # !_LC3_B1 & !_LC4_B1
         #  _LC1_B11 & !_LC3_B1
         #  _LC3_B1 &  _LC4_B1
         #  _LC1_B11 &  _LC4_B1;

-- Node name is '|alu8:47|BCD_7SEG:81|:639' 
-- Equation name is '_LC8_A2', type is buried 
_LC8_A2  = LCELL( _EQ008);
  _EQ008 = !_LC1_A11 & !_LC3_B1 & !_LC4_B1
         #  _LC6_A2;

-- Node name is '|alu8:47|BCD_7SEG:81|:641' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = LCELL( _EQ009);
  _EQ009 = !_LC2_A2 &  _LC3_A2
         # !_LC2_A2 &  _LC4_A2 & !_LC5_A2;

-- Node name is '|alu8:47|BCD_7SEG:81|:687' 
-- Equation name is '_LC5_A11', type is buried 
_LC5_A11 = LCELL( _EQ010);
  _EQ010 =  _LC1_B11 & !_LC3_B1 & !_LC4_B1
         # !_LC1_B1 & !_LC3_B1 & !_LC4_B1
         # !_LC1_B1 &  _LC1_B11 & !_LC4_B1
         # !_LC1_B1 & !_LC1_B11 & !_LC3_B1
         #  _LC1_B1 & !_LC1_B11 &  _LC3_B1
         # !_LC1_B1 & !_LC1_B11 &  _LC4_B1
         # !_LC1_B1 &  _LC1_B11 &  _LC3_B1
         #  _LC1_B1 &  _LC1_B11 & !_LC3_B1;

-- Node name is '|alu8:47|BCD_7SEG:81|:735' 
-- Equation name is '_LC4_A1', type is buried 
_LC4_A1  = LCELL( _EQ011);
  _EQ011 = !_LC1_B11 & !_LC3_B1
         #  _LC3_B1 & !_LC4_B1
         # !_LC1_B11 & !_LC4_B1
         #  _LC1_B1 & !_LC4_B1
         # !_LC3_B1 &  _LC4_B1
         #  _LC1_B1 & !_LC1_B11;

-- Node name is '|alu8:47|BCD_7SEG:81|:755' 
-- Equation name is '_LC6_A1', type is buried 
_LC6_A1  = LCELL( _EQ012);
  _EQ012 =  _LC1_B1 & !_LC1_B11 &  _LC3_B1 &  _LC4_B1
         # !_LC1_B1 &  _LC1_B11 &  _LC3_B1 &  _LC4_B1;

-- Node name is '|alu8:47|BCD_7SEG:81|:773' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ013);
  _EQ013 =  _LC2_A1 & !_LC5_A1
         # !_LC5_A1 &  _LC6_A1;

-- Node name is '|alu8:47|BCD_7SEG:81|~783~1' 
-- Equation name is '_LC5_A2', type is buried 
-- synthesized logic cell 
!_LC5_A2 = _LC5_A2~NOT;
_LC5_A2~NOT = LCELL( _EQ014);
  _EQ014 =  _LC4_B1
         # !_LC1_B11 & !_LC3_B1
         #  _LC1_B1 & !_LC1_B11
         # !_LC1_B1 & !_LC3_B1
         # !_LC1_B1 &  _LC1_B11
         #  _LC1_B11 &  _LC3_B1