zongtu.rpt
来自「用verilog语言写的拔河游戏机」· RPT 代码 · 共 1,215 行 · 第 1/5 页
RPT
1,215 行
B23 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
B24 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 14/22( 63%)
C2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
C10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
C13 4/ 8( 50%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
C16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C19 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
C21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C24 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
B25 8/8 (100%) 0/8 ( 0%) 8/8 (100%) 1/2 2/2 17/22( 77%)
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 50/53 ( 94%)
Total logic cells used: 188/576 ( 32%)
Total embedded cells used: 8/24 ( 33%)
Total EABs used: 1/3 ( 33%)
Average fan-in: 2.95/4 ( 73%)
Total fan-in: 556/2304 ( 24%)
Total input pins required: 26
Total input I/O cell registers required: 0
Total output pins required: 22
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 188
Total flipflops required: 68
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 45/ 576 ( 7%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 0 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19/0
B: 8 8 8 2 8 1 8 4 8 8 8 8 8 8 8 6 7 8 1 8 4 8 8 6 8 159/8
C: 0 1 0 0 0 0 0 0 0 1 0 0 0 4 0 0 1 0 0 1 0 1 0 0 1 10/0
Total: 16 17 8 2 9 1 8 4 8 9 10 8 8 12 8 6 8 8 1 9 4 9 8 6 9 188/8
Device-Specific Information: e:\xyq\maxplus\sy4\zongtu.rpt
zongtu
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
42 - - - -- INPUT 0 0 0 9 ALU_BUS
11 - - - 01 INPUT 0 0 0 16 cir_cdu
48 - - - 15 INPUT 0 0 0 4 cir_181
1 - - - -- INPUT G 0 0 0 1 clk_cdu
53 - - - 20 INPUT 0 0 0 2 CN
37 - - - 09 INPUT 0 0 0 1 cpldar
62 - - C -- INPUT 0 0 0 4 CP_T
21 - - B -- BIDIR 0 1 0 7 dout0
65 - - B -- BIDIR 0 1 0 7 dout1
36 - - - 07 BIDIR 0 1 0 7 dout2
5 - - - 05 BIDIR 0 1 0 7 dout3
67 - - B -- BIDIR 0 1 0 7 dout4
79 - - - 24 BIDIR 0 1 0 7 dout5
22 - - B -- BIDIR 0 1 0 7 dout6
83 - - - 13 BIDIR 0 1 0 7 dout7
3 - - - 12 INPUT 0 0 0 9 enable
10 - - - 01 INPUT 0 0 0 8 encdu
50 - - - 17 INPUT 0 0 0 3 en_181
39 - - - 11 INPUT 0 0 0 1 LDAR
59 - - C -- INPUT 0 0 0 1 LDDR1
30 - - C -- INPUT 0 0 0 1 LDDR2
29 - - C -- INPUT 0 0 0 1 LDR4
27 - - C -- INPUT 0 0 0 1 LDR5
84 - - - -- INPUT 0 0 0 8 M
66 - - B -- INPUT 0 0 0 9 pc_bus
44 - - - -- INPUT 0 0 0 10 RD
47 - - - 14 INPUT 0 0 0 9 R4_BUS
43 - - - -- INPUT 0 0 0 9 R5_BUS
49 - - - 16 INPUT 0 0 0 6 scan_clk
35 - - - 06 INPUT 0 0 0 9 sw_bus
73 - - A -- INPUT 0 0 0 1 WE
2 - - - -- INPUT G 0 0 0 0 161clr
52 - - - 19 INPUT 0 0 0 8 161load
38 - - - 10 INPUT 0 0 0 1 161pc
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\xyq\maxplus\sy4\zongtu.rpt
zongtu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
23 - - B -- OUTPUT 0 1 0 0 adr0
28 - - C -- OUTPUT 0 1 0 0 adr1
25 - - B -- OUTPUT 0 1 0 0 adr2
7 - - - 03 OUTPUT 0 1 0 0 adr3
6 - - - 04 OUTPUT 0 1 0 0 adr4
80 - - - 23 OUTPUT 0 1 0 0 adr5
8 - - - 03 OUTPUT 0 1 0 0 adr6
24 - - B -- OUTPUT 0 1 0 0 adr7
51 - - - 18 OUTPUT 0 1 0 0 cn4
21 - - B -- TRI 0 1 0 7 dout0
65 - - B -- TRI 0 1 0 7 dout1
36 - - - 07 TRI 0 1 0 7 dout2
5 - - - 05 TRI 0 1 0 7 dout3
67 - - B -- TRI 0 1 0 7 dout4
79 - - - 24 TRI 0 1 0 7 dout5
22 - - B -- TRI 0 1 0 7 dout6
83 - - - 13 TRI 0 1 0 7 dout7
19 - - A -- OUTPUT 0 1 0 0 indata_a
16 - - A -- OUTPUT 0 1 0 0 indata_b
71 - - A -- OUTPUT 0 1 0 0 indata_c
18 - - A -- OUTPUT 0 1 0 0 indata_d
69 - - A -- OUTPUT 0 1 0 0 indata-f
17 - - A -- OUTPUT 0 1 0 0 indata_g
58 - - C -- OUTPUT 0 1 0 0 indata_gw
61 - - C -- OUTPUT 0 1 0 0 indata_sw
70 - - A -- OUTPUT 0 1 0 0 ndata_e
81 - - - 22 OUTPUT 0 1 0 0 s0
64 - - B -- OUTPUT 0 1 0 0 s1
72 - - A -- OUTPUT 0 1 0 0 s2
54 - - - 21 OUTPUT 0 1 0 0 s3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\xyq\maxplus\sy4\zongtu.rpt
zongtu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 11 AND2 s ! 0 2 0 2 |alu8:47|BCD_7SEG:81|~492~1
- 3 - A 02 AND2 0 4 0 2 |alu8:47|BCD_7SEG:81|:516
- 2 - A 02 OR2 ! 0 4 0 2 |alu8:47|BCD_7SEG:81|:528
- 3 - A 01 OR2 0 4 1 0 |alu8:47|BCD_7SEG:81|:545
- 5 - A 01 OR2 s ! 0 4 0 1 |alu8:47|BCD_7SEG:81|~579~1
- 8 - A 01 OR2 0 4 1 0 |alu8:47|BCD_7SEG:81|:591
- 4 - A 02 OR2 s 0 4 0 1 |alu8:47|BCD_7SEG:81|~635~1
- 8 - A 02 OR2 0 4 1 0 |alu8:47|BCD_7SEG:81|:639
- 6 - A 02 OR2 0 4 0 1 |alu8:47|BCD_7SEG:81|:641
- 5 - A 11 OR2 0 4 1 0 |alu8:47|BCD_7SEG:81|:687
- 4 - A 01 OR2 0 4 1 0 |alu8:47|BCD_7SEG:81|:735
- 6 - A 01 OR2 0 4 0 1 |alu8:47|BCD_7SEG:81|:755
- 1 - A 01 OR2 0 3 0 1 |alu8:47|BCD_7SEG:81|:773
- 5 - A 02 OR2 s ! 0 4 0 2 |alu8:47|BCD_7SEG:81|~783~1
- 7 - A 02 OR2 s 0 4 0 1 |alu8:47|BCD_7SEG:81|~783~2
- 1 - A 02 OR2 0 4 1 0 |alu8:47|BCD_7SEG:81|:783
- 2 - A 01 OR2 s 0 4 0 1 |alu8:47|BCD_7SEG:81|~816~1
- 7 - A 01 OR2 0 4 1 0 |alu8:47|BCD_7SEG:81|:831
- 1 - B 22 DFFE + 2 0 1 10 |alu8:47|cdu16:50|74163:8|f74163:sub|QA (|alu8:47|cdu16:50|74163:8|f74163:sub|:34)
- 6 - B 22 DFFE + 2 1 1 9 |alu8:47|cdu16:50|74163:8|f74163:sub|QB (|alu8:47|cdu16:50|74163:8|f74163:sub|:111)
- 8 - B 22 AND2 1 2 0 2 |alu8:47|cdu16:50|74163:8|f74163:sub|:119
- 2 - B 22 DFFE + 1 1 1 9 |alu8:47|cdu16:50|74163:8|f74163:sub|QC (|alu8:47|cdu16:50|74163:8|f74163:sub|:122)
- 5 - B 22 DFFE + 1 2 1 8 |alu8:47|cdu16:50|74163:8|f74163:sub|QD (|alu8:47|cdu16:50|74163:8|f74163:sub|:134)
- 2 - B 11 DFFE + 2 0 0 6 |alu8:47|cdu16:54|74163:8|f74163:sub|QA (|alu8:47|cdu16:54|74163:8|f74163:sub|:34)
- 7 - B 11 AND2 0 2 0 1 |alu8:47|cdu16:54|74163:8|f74163:sub|:106
- 4 - B 11 DFFE + 2 1 0 5 |alu8:47|cdu16:54|74163:8|f74163:sub|QB (|alu8:47|cdu16:54|74163:8|f74163:sub|:111)
- 6 - B 11 AND2 0 3 0 1 |alu8:47|cdu16:54|74163:8|f74163:sub|:117
- 3 - B 11 DFFE + 2 1 0 4 |alu8:47|cdu16:54|74163:8|f74163:sub|QC (|alu8:47|cdu16:54|74163:8|f74163:sub|:122)
- 8 - B 11 AND2 0 4 0 3 |alu8:47|cdu16:54|74163:8|f74163:sub|:128
- 5 - B 11 DFFE + 2 1 0 3 |alu8:47|cdu16:54|74163:8|f74163:sub|QD (|alu8:47|cdu16:54|74163:8|f74163:sub|:134)
- 5 - B 01 DFFE + 1 1 0 4 |alu8:47|cdu16:56|74163:8|f74163:sub|QA (|alu8:47|cdu16:56|74163:8|f74163:sub|:34)
- 8 - B 01 DFFE + 1 2 0 3 |alu8:47|cdu16:56|74163:8|f74163:sub|QB (|alu8:47|cdu16:56|74163:8|f74163:sub|:111)
- 7 - B 01 AND2 0 3 0 2 |alu8:47|cdu16:56|74163:8|f74163:sub|:119
- 6 - B 01 DFFE + 1 1 0 3 |alu8:47|cdu16:56|74163:8|f74163:sub|QC (|alu8:47|cdu16:56|74163:8|f74163:sub|:122)
- 2 - B 01 DFFE + 1 2 0 2 |alu8:47|cdu16:56|74163:8|f74163:sub|QD (|alu8:47|cdu16:56|74163:8|f74163:sub|:134)
- 1 - B 01 OR2 1 2 0 13 |alu8:47|saomiao:78|74157:1|Y1 (|alu8:47|saomiao:78|74157:1|:22)
- 1 - B 11 OR2 1 2 0 13 |alu8:47|saomiao:78|74157:1|Y2 (|alu8:47|saomiao:78|74157:1|:23)
- 3 - B 01 OR2 1 2 0 14 |alu8:47|saomiao:78|74157:1|Y3 (|alu8:47|saomiao:78|74157:1|:24)
- 4 - B 01 OR2 1 2 0 14 |alu8:47|saomiao:78|74157:1|Y4 (|alu8:47|saomiao:78|74157:1|:25)
- 4 - C 13 AND2 2 0 0 8 |alu8:47|:6
- 6 - C 13 AND2 2 0 0 8 |alu8:47|:7
- 1 - C 13 AND2 2 0 0 8 |alu8:47|:8
- 2 - C 13 AND2 2 0 0 8 |alu8:47|:9
- 3 - B 22 OR2 0 4 0 3 |alu8:47|74181:46|:43
- 2 - B 24 OR2 0 4 0 2 |alu8:47|74181:46|:44
- 2 - B 13 OR2 ! 0 4 0 3 |alu8:47|74181:46|:45
- 4 - B 22 OR2 0 4 0 2 |alu8:47|74181:46|:46
- 3 - B 24 OR2 0 4 0 2 |alu8:47|74181:46|:47
- 3 - B 13 OR2 ! 0 4 0 2 |alu8:47|74181:46|:48
- 3 - B 17 OR2 0 4 0 2 |alu8:47|74181:46|:51
- 2 - B 17 OR2 0 4 0 2 |alu8:47|74181:46|:52
- 2 - B 16 OR2 s 0 4 0 2 |alu8:47|74181:46|~66~1
- 4 - B 17 OR2 s 0 2 0 2 |alu8:47|74181:46|~74~1
- 5 - B 17 OR2 1 2 0 1 |alu8:47|74181:46|:74
- 1 - B 24 OR2 s 0 4 0 2 |alu8:47|74181:46|~75~1
- 6 - B 17 OR2 0 4 1 0 |alu8:47|74181:46|CN4 (|alu8:47|74181:46|:78)
- 4 - B 24 OR2 1 2 0 1 |alu8:47|74181:46|:79
- 5 - B 16 OR2 1 3 0 1 |alu8:47|74181:46|:80
- 1 - B 17 OR2 1 3 0 1 |alu8:47|74181:46|:82
- 2 - B 21 OR2 ! 0 4 0 2 |alu8:47|74181:47|:43
- 2 - B 19 OR2 ! 0 4 0 2 |alu8:47|74181:47|:44
- 3 - B 21 OR2 ! 0 4 0 2 |alu8:47|74181:47|:45
- 4 - B 21 OR2 ! 0 4 0 2 |alu8:47|74181:47|:46
- 1 - B 19 OR2 ! 0 4 0 2 |alu8:47|74181:47|:47
- 6 - B 21 OR2 ! 0 4 0 2 |alu8:47|74181:47|:48
- 1 - B 13 OR2 ! 0 4 0 3 |alu8:47|74181:47|:51
- 4 - B 13 OR2 ! 0 4 0 3 |alu8:47|74181:47|:52
- 3 - B 19 OR2 s 1 2 0 2 |alu8:47|74181:47|~74~1
- 7 - B 16 OR2 1 3 0 1 |alu8:47|74181:47|:77
- 8 - B 19 OR2 s 0 3 0 2 |alu8:47|74181:47|CN4~1 (|alu8:47|74181:47|~78~1)
- 1 - B 21 OR2 s 0 3 0 3 |alu8:47|74181:47|CN4~2 (|alu8:47|74181:47|~78~2)
- 4 - B 16 OR2 ! 0 3 0 1 |alu8:47|74181:47|CN4 (|alu8:47|74181:47|:78)
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