📄 zongtu.rpt
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- 5 - B 10 OR2 s 2 1 0 1 |alu8:47|74181:47|~80~1
- 4 - B 19 OR2 1 3 0 1 |alu8:47|74181:47|:81
- 5 - B 21 OR2 1 3 0 1 |alu8:47|74181:47|:82
- 6 - B 10 OR2 1 2 0 1 |alu8:47|74244:48|~1~2
- 8 - B 17 OR2 1 3 0 1 |alu8:47|74244:48|~26~2
- 5 - B 24 OR2 1 3 0 1 |alu8:47|74244:48|~31~2
- 1 - B 20 DFFE 0 2 0 2 |alu8:47|74273:44|Q8 (|alu8:47|74273:44|:12)
- 8 - B 13 DFFE 0 2 0 2 |alu8:47|74273:44|Q7 (|alu8:47|74273:44|:13)
- 7 - B 24 DFFE 0 2 0 2 |alu8:47|74273:44|Q6 (|alu8:47|74273:44|:14)
- 2 - B 20 DFFE 0 2 0 2 |alu8:47|74273:44|Q5 (|alu8:47|74273:44|:15)
- 6 - B 13 DFFE 0 2 0 2 |alu8:47|74273:44|Q4 (|alu8:47|74273:44|:16)
- 8 - B 21 DFFE 0 2 0 2 |alu8:47|74273:44|Q3 (|alu8:47|74273:44|:17)
- 3 - B 20 DFFE 0 2 0 2 |alu8:47|74273:44|Q2 (|alu8:47|74273:44|:18)
- 4 - B 20 DFFE 0 2 0 2 |alu8:47|74273:44|Q1 (|alu8:47|74273:44|:19)
- 7 - B 17 DFFE 0 2 0 2 |alu8:47|74273:45|Q8 (|alu8:47|74273:45|:12)
- 7 - B 13 DFFE 0 2 0 2 |alu8:47|74273:45|Q7 (|alu8:47|74273:45|:13)
- 6 - B 24 DFFE 0 2 0 2 |alu8:47|74273:45|Q6 (|alu8:47|74273:45|:14)
- 7 - B 22 DFFE 0 2 0 2 |alu8:47|74273:45|Q5 (|alu8:47|74273:45|:15)
- 5 - B 13 DFFE 0 2 0 2 |alu8:47|74273:45|Q4 (|alu8:47|74273:45|:16)
- 7 - B 21 DFFE 0 2 0 2 |alu8:47|74273:45|Q3 (|alu8:47|74273:45|:17)
- 7 - B 19 DFFE 0 2 0 2 |alu8:47|74273:45|Q2 (|alu8:47|74273:45|:18)
- 4 - B 18 DFFE 0 2 0 2 |alu8:47|74273:45|Q1 (|alu8:47|74273:45|:19)
- 8 - B 10 DFFE 0 2 0 1 |alu8:47|74374:42|:13
- 7 - B 09 DFFE 0 2 0 1 |alu8:47|74374:42|:14
- 3 - B 12 DFFE 0 2 0 1 |alu8:47|74374:42|:15
- 6 - B 05 DFFE 0 2 0 1 |alu8:47|74374:42|:16
- 2 - B 09 DFFE 0 2 0 1 |alu8:47|74374:42|:17
- 4 - B 15 DFFE 0 2 0 1 |alu8:47|74374:42|:18
- 6 - B 15 DFFE 0 2 0 1 |alu8:47|74374:42|:19
- 3 - B 14 DFFE 0 2 0 1 |alu8:47|74374:42|:20
- 7 - B 10 DFFE 0 2 0 1 |alu8:47|74374:43|:13
- 6 - B 09 DFFE 0 2 0 1 |alu8:47|74374:43|:14
- 2 - C 02 DFFE 0 2 0 1 |alu8:47|74374:43|:15
- 4 - C 10 DFFE 0 2 0 1 |alu8:47|74374:43|:16
- 1 - B 09 DFFE 0 2 0 1 |alu8:47|74374:43|:17
- 3 - B 15 DFFE 0 2 0 1 |alu8:47|74374:43|:18
- 5 - B 15 DFFE 0 2 0 1 |alu8:47|74374:43|:19
- 4 - C 19 DFFE 0 2 0 1 |alu8:47|74374:43|:20
- 7 - C 21 LCELL s 1 0 1 0 indata_gw~1
- 2 - C 16 LCELL s 1 0 1 0 indata_sw~1
- 4 - B 07 DFFE + 2 0 0 4 |test_ram:1|cdu16:74|74163:8|f74163:sub|QA (|test_ram:1|cdu16:74|74163:8|f74163:sub|:34)
- 8 - B 07 AND2 0 2 0 1 |test_ram:1|cdu16:74|74163:8|f74163:sub|:106
- 7 - B 07 DFFE + 2 1 0 3 |test_ram:1|cdu16:74|74163:8|f74163:sub|QB (|test_ram:1|cdu16:74|74163:8|f74163:sub|:111)
- 2 - B 07 DFFE + 2 1 0 2 |test_ram:1|cdu16:74|74163:8|f74163:sub|QC (|test_ram:1|cdu16:74|74163:8|f74163:sub|:122)
- 6 - B 07 AND2 1 3 0 2 |test_ram:1|cdu16:74|74163:8|f74163:sub|:130
- 5 - B 07 DFFE + 1 1 0 2 |test_ram:1|cdu16:74|74163:8|f74163:sub|QD (|test_ram:1|cdu16:74|74163:8|f74163:sub|:134)
- 5 - B 02 DFFE + 1 1 0 3 |test_ram:1|cdu16:75|74163:8|f74163:sub|QA (|test_ram:1|cdu16:75|74163:8|f74163:sub|:34)
- 6 - B 02 DFFE + 1 2 0 2 |test_ram:1|cdu16:75|74163:8|f74163:sub|QB (|test_ram:1|cdu16:75|74163:8|f74163:sub|:111)
- 4 - B 02 AND2 0 3 0 2 |test_ram:1|cdu16:75|74163:8|f74163:sub|:119
- 7 - B 02 DFFE + 1 1 0 2 |test_ram:1|cdu16:75|74163:8|f74163:sub|QC (|test_ram:1|cdu16:75|74163:8|f74163:sub|:122)
- 2 - B 02 DFFE + 1 2 0 1 |test_ram:1|cdu16:75|74163:8|f74163:sub|QD (|test_ram:1|cdu16:75|74163:8|f74163:sub|:134)
- - 2 B -- MEM_SGMT 0 10 0 1 |test_ram:1|LPM_RAM_IO:57|altram:sram|segment0_0
- - 3 B -- MEM_SGMT 0 10 0 1 |test_ram:1|LPM_RAM_IO:57|altram:sram|segment0_1
- - 8 B -- MEM_SGMT 0 10 0 1 |test_ram:1|LPM_RAM_IO:57|altram:sram|segment0_2
- - 6 B -- MEM_SGMT 0 10 0 1 |test_ram:1|LPM_RAM_IO:57|altram:sram|segment0_3
- - 1 B -- MEM_SGMT 0 10 0 1 |test_ram:1|LPM_RAM_IO:57|altram:sram|segment0_4
- - 4 B -- MEM_SGMT 0 10 0 1 |test_ram:1|LPM_RAM_IO:57|altram:sram|segment0_5
- - 7 B -- MEM_SGMT 0 10 0 1 |test_ram:1|LPM_RAM_IO:57|altram:sram|segment0_6
- - 5 B -- MEM_SGMT 0 10 0 1 |test_ram:1|LPM_RAM_IO:57|altram:sram|segment0_7
- 2 - B 10 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri0~1~2~3~3
- 3 - B 10 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri0~1~2~3~4
- 4 - B 10 OR2 s 1 3 0 1 |test_ram:1|LPM_RAM_IO:57|datatri0~1~2~3~5
- 1 - B 10 OR2 1 3 1 0 |test_ram:1|LPM_RAM_IO:57|datatri0~1~2~3
- 5 - B 09 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri1~1~2~3~3
- 8 - B 09 OR2 s 1 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri1~1~2~3~4
- 3 - B 07 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri1~1~2~3~5
- 6 - B 19 OR2 s 1 3 0 1 |test_ram:1|LPM_RAM_IO:57|datatri1~1~2~3~6
- 5 - B 19 OR2 1 2 1 0 |test_ram:1|LPM_RAM_IO:57|datatri1~1~2~3
- 1 - B 12 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri2~1~2~3~3
- 4 - B 12 OR2 s 1 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri2~1~2~3~4
- 1 - B 08 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri2~1~2~3~5
- 2 - B 08 OR2 s 1 3 0 1 |test_ram:1|LPM_RAM_IO:57|datatri2~1~2~3~6
- 6 - B 08 OR2 1 2 1 0 |test_ram:1|LPM_RAM_IO:57|datatri2~1~2~3
- 3 - B 09 OR2 s 4 0 0 1 |test_ram:1|LPM_RAM_IO:57|datatri3~1~2~2~2
- 4 - B 08 OR2 3 1 0 0 |test_ram:1|LPM_RAM_IO:57|datatri3~1~2~2
- 3 - B 05 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri3~1~2~3~3
- 4 - B 05 OR2 s 1 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri3~1~2~3~4
- 5 - B 05 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri3~1~2~3~5
- 3 - B 16 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri3~1~2~3~6
- 1 - B 05 AND2 0 3 1 0 |test_ram:1|LPM_RAM_IO:57|datatri3~1~2~3
- 4 - B 09 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri4~1~2~3~3
- 2 - B 23 OR2 s 1 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri4~1~2~3~4
- 8 - B 02 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri4~1~2~3~5
- 6 - B 16 OR2 s 1 3 0 1 |test_ram:1|LPM_RAM_IO:57|datatri4~1~2~3~6
- 1 - B 16 OR2 1 2 1 0 |test_ram:1|LPM_RAM_IO:57|datatri4~1~2~3
- 1 - B 15 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri5~1~2~3~3
- 3 - B 02 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri5~1~2~3~4
- 1 - B 23 OR2 s 1 3 0 1 |test_ram:1|LPM_RAM_IO:57|datatri5~1~2~3~5
- 8 - B 24 OR2 1 3 1 0 |test_ram:1|LPM_RAM_IO:57|datatri5~1~2~3
- 2 - B 15 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri6~1~2~3~3
- 6 - B 14 OR2 s 1 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri6~1~2~3~4
- 1 - B 02 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri6~1~2~3~5
- 1 - B 04 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri6~1~2~3~6
- 2 - B 04 AND2 0 3 1 0 |test_ram:1|LPM_RAM_IO:57|datatri6~1~2~3
- 1 - B 14 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri7~1~2~3~3
- 4 - B 06 OR2 s 2 2 0 1 |test_ram:1|LPM_RAM_IO:57|datatri7~1~2~3~4
- 2 - B 14 OR2 s 1 3 0 1 |test_ram:1|LPM_RAM_IO:57|datatri7~1~2~3~5
- 8 - B 14 OR2 1 3 1 0 |test_ram:1|LPM_RAM_IO:57|datatri7~1~2~3
- 1 - A 05 AND2 2 0 0 8 |test_ram:1|LPM_RAM_IO:57|:90
- 1 - B 07 AND2 0 2 0 3 |test_ram:1|:60
- 5 - B 03 AND2 2 0 0 8 |test_ram:1|:80
- 6 - B 12 AND2 2 0 0 8 |test_ram:1|:81
- 2 - B 12 DFFE 1 2 0 5 |test_ram:1|74161:116|f74161:sub|QA (|test_ram:1|74161:116|f74161:sub|:9)
- 8 - B 12 AND2 0 2 0 1 |test_ram:1|74161:116|f74161:sub|:84
- 7 - B 12 DFFE 1 3 0 4 |test_ram:1|74161:116|f74161:sub|QB (|test_ram:1|74161:116|f74161:sub|:87)
- 7 - B 05 AND2 0 3 0 1 |test_ram:1|74161:116|f74161:sub|:94
- 5 - B 12 DFFE 1 3 0 3 |test_ram:1|74161:116|f74161:sub|QC (|test_ram:1|74161:116|f74161:sub|:99)
- 2 - B 05 AND2 0 4 0 2 |test_ram:1|74161:116|f74161:sub|:104
- 8 - B 05 DFFE 1 3 0 2 |test_ram:1|74161:116|f74161:sub|QD (|test_ram:1|74161:116|f74161:sub|:110)
- 3 - B 23 DFFE 1 3 0 2 |test_ram:1|74161:117|f74161:sub|QA (|test_ram:1|74161:117|f74161:sub|:9)
- 5 - B 23 AND2 0 2 0 2 |test_ram:1|74161:117|f74161:sub|:80
- 4 - B 23 AND2 0 2 0 2 |test_ram:1|74161:117|f74161:sub|:84
- 6 - B 23 DFFE 1 3 0 2 |test_ram:1|74161:117|f74161:sub|QB (|test_ram:1|74161:117|f74161:sub|:87)
- 4 - B 14 AND2 0 2 0 1 |test_ram:1|74161:117|f74161:sub|:94
- 7 - B 14 DFFE 1 3 0 2 |test_ram:1|74161:117|f74161:sub|QC (|test_ram:1|74161:117|f74161:sub|:99)
- 5 - B 14 DFFE 1 3 0 1 |test_ram:1|74161:117|f74161:sub|QD (|test_ram:1|74161:117|f74161:sub|:110)
- 6 - B 03 DFFE 0 2 1 8 |test_ram:1|74273:115|Q8 (|test_ram:1|74273:115|:12)
- 1 - B 03 DFFE 0 2 1 8 |test_ram:1|74273:115|Q7 (|test_ram:1|74273:115|:13)
- 4 - C 24 DFFE 0 2 1 8 |test_ram:1|74273:115|Q6 (|test_ram:1|74273:115|:14)
- 7 - B 03 DFFE 0 2 1 8 |test_ram:1|74273:115|Q5 (|test_ram:1|74273:115|:15)
- 2 - B 03 DFFE 0 2 1 8 |test_ram:1|74273:115|Q4 (|test_ram:1|74273:115|:16)
- 8 - B 03 DFFE 0 2 1 8 |test_ram:1|74273:115|Q3 (|test_ram:1|74273:115|:17)
- 3 - B 03 DFFE 0 2 1 8 |test_ram:1|74273:115|Q2 (|test_ram:1|74273:115|:18)
- 4 - B 03 DFFE 0 2 1 8 |test_ram:1|74273:115|Q1 (|test_ram:1|74273:115|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\xyq\maxplus\sy4\zongtu.rpt
zongtu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 7/ 48( 14%) 1/ 48( 2%) 1/16( 6%) 8/16( 50%) 0/16( 0%)
B: 52/ 96( 54%) 33/ 48( 68%) 27/ 48( 56%) 1/16( 6%) 4/16( 25%) 4/16( 25%)
C: 7/ 96( 7%) 3/ 48( 6%) 5/ 48( 10%) 5/16( 31%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 5/24( 20%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
14: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\xyq\maxplus\sy4\zongtu.rpt
zongtu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 29 clk_cdu
LCELL 8 |alu8:47|:6
LCELL 8 |alu8:47|:7
LCELL 8 |alu8:47|:8
LCELL 8 |alu8:47|:9
LCELL 8 |test_ram:1|:80
LCELL 8 |test_ram:1|:81
Device-Specific Information: e:\xyq\maxplus\sy4\zongtu.rpt
zongtu
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 161clr
Device-Specific Information: e:\xyq\maxplus\sy4\zongtu.rpt
zongtu
** EQUATIONS **
ALU_BUS : INPUT;
cir_cdu : INPUT;
cir_181 : INPUT;
clk_cdu : INPUT;
CN : INPUT;
cpldar : INPUT;
CP_T : INPUT;
enable : INPUT;
encdu : INPUT;
en_181 : INPUT;
LDAR : INPUT;
LDDR1 : INPUT;
LDDR2 : INPUT;
LDR4 : INPUT;
LDR5 : INPUT;
M : INPUT;
pc_bus : INPUT;
RD : INPUT;
R4_BUS : INPUT;
R5_BUS : INPUT;
scan_clk : INPUT;
sw_bus : INPUT;
WE : INPUT;
161clr : INPUT;
161load : INPUT;
161pc : INPUT;
-- Node name is 'adr0'
-- Equation name is 'adr0', type is output
adr0 = _LC4_B3;
-- Node name is 'adr1'
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