floor_select.hier_info

《Verilog HDL数字控制系统设计实例》-冼进-源代码

|Floor_Select
Reset => always0~0.IN0
En => always0~0.IN1
num1 => always0~1.IN0
num2 => always0~2.IN0
num3 => always0~4.IN0
num4 => always0~6.IN0
num5 => always0~8.IN0
num6 => always0~10.IN0
num7 => always0~14.IN0
num8 => always0~16.IN0
num9 => always0~20.IN0
now_floor[0] => reduce_nor~1.IN2
now_floor[0] => reduce_nor~3.IN2
now_floor[0] => reduce_nor~5.IN1
now_floor[0] => reduce_nor~7.IN2
now_floor[0] => always0~18.IN0
now_floor[1] => reduce_nor~0.IN2
now_floor[1] => reduce_nor~3.IN1
now_floor[1] => reduce_nor~4.IN1
now_floor[1] => always0~12.IN0
now_floor[1] => reduce_nor~7.IN1
now_floor[1] => reduce_nor~8.IN1
now_floor[2] => reduce_nor~0.IN1
now_floor[2] => reduce_nor~1.IN1
now_floor[2] => reduce_nor~2.IN1
now_floor[2] => always0~13.IN0
now_floor[2] => reduce_nor~7.IN0
now_floor[2] => reduce_nor~8.IN0
now_floor[3] => reduce_nor~0.IN0
now_floor[3] => reduce_nor~1.IN0
now_floor[3] => reduce_nor~2.IN0
now_floor[3] => reduce_nor~3.IN0
now_floor[3] => reduce_nor~4.IN0
now_floor[3] => reduce_nor~5.IN0
now_floor[3] => reduce_nor~6.IN0
now_floor[3] => always0~19.IN0
floor_arrive <= floor_arrive~0.DB_MAX_OUTPUT_PORT_TYPE