master_control_main.tan.qmsg

《Verilog HDL数字控制系统设计实例》-冼进-源代码

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Lift_Run_Manage:inst2\|Down_En~28 " "Info: Node \"Lift_Run_Manage:inst2\|Down_En~28\"" {  } { { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Lift_Run_Manage.v" 53 -1 0 } }  } 0}  } { { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Master_Control_Main/Lift_Run_Manage.v" 53 -1 0 } }  } 0}