lift_run_manage.tan.qmsg

《Verilog HDL数字控制系统设计实例》-冼进-源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 07 20:44:31 2006 " "Info: Processing started: Mon Aug 07 20:44:31 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Lift_Run_Manage -c Lift_Run_Manage " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Lift_Run_Manage -c Lift_Run_Manage" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Up_En\$latch~10 " "Info: Node \"Up_En\$latch~10\"" {  } { { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/Lift_Run_Manage.v" 68 -1 0 } }  } 0}  } { { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/Lift_Run_Manage.v" 68 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Down_En\$latch~10 " "Info: Node \"Down_En\$latch~10\"" {  } { { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/Lift_Run_Manage.v" 68 -1 0 } }  } 0}  } { { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/Lift_Run_Manage.v" 68 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Now_Floor\[3\] Up_En 17.100 ns Longest " "Info: Longest tpd from source pin \"Now_Floor\[3\]\" to destination pin \"Up_En\" is 17.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Now_Floor\[3\] 1 PIN PIN_50 37 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_50; Fanout = 37; PIN Node = 'Now_Floor\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" Compiler "Lift_Run_Manage" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/" "" "" { Now_Floor[3] } "NODE_NAME" } "" } } { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/Lift_Run_Manage.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(4.000 ns) 5.900 ns always0~1124 2 COMB LC29 2 " "Info: 2: + IC(1.700 ns) + CELL(4.000 ns) = 5.900 ns; Loc. = LC29; Fanout = 2; COMB Node = 'always0~1124'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" Compiler "Lift_Run_Manage" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/" "" "5.700 ns" { Now_Floor[3] always0~1124 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(4.000 ns) 11.300 ns always0~1191 3 COMB LC2 3 " "Info: 3: + IC(1.400 ns) + CELL(4.000 ns) = 11.300 ns; Loc. = LC2; Fanout = 3; COMB Node = 'always0~1191'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" Compiler "Lift_Run_Manage" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/" "" "5.400 ns" { always0~1124 always0~1191 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.400 ns) 16.700 ns Up_En\$latch~10 4 COMB LOOP LC1 3 " "Info: 4: + IC(0.000 ns) + CELL(5.400 ns) = 16.700 ns; Loc. = LC1; Fanout = 3; COMB LOOP Node = 'Up_En\$latch~10'" { { "Info" "ITDB_PART_OF_SCC" "Up_En\$latch~10 LC1 " "Info: Loc. = LC1; Node \"Up_En\$latch~10\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" Compiler "Lift_Run_Manage" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/" "" "" { Up_En$latch~10 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" Compiler "Lift_Run_Manage" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/" "" "" { Up_En$latch~10 } "NODE_NAME" } "" } } { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/Lift_Run_Manage.v" 68 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" Compiler "Lift_Run_Manage" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/" "" "5.400 ns" { always0~1191 Up_En$latch~10 } "NODE_NAME" } "" } } { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/Lift_Run_Manage.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 17.100 ns Up_En 5 PIN PIN_2 0 " "Info: 5: + IC(0.000 ns) + CELL(0.400 ns) = 17.100 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'Up_En'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" Compiler "Lift_Run_Manage" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/" "" "0.400 ns" { Up_En$latch~10 Up_En } "NODE_NAME" } "" } } { "Lift_Run_Manage.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/Lift_Run_Manage.v" 52 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 81.87 % " "Info: Total cell delay = 14.000 ns ( 81.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns 18.13 % " "Info: Total interconnect delay = 3.100 ns ( 18.13 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage_cmp.qrpt" Compiler "Lift_Run_Manage" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/db/Lift_Run_Manage.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Lift_Run_Manage/" "" "17.100 ns" { Now_Floor[3] always0~1124 always0~1191 Up_En$latch~10 Up_En } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.100 ns" { Now_Floor[3] Now_Floor[3]~out always0~1124 always0~1191 Up_En$latch~10 Up_En } { 0.000ns 0.000ns 1.700ns 1.400ns 0.000ns 0.000ns } { 0.000ns 0.200ns 4.000ns 4.000ns 5.400ns 0.400ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 07 20:44:32 2006 " "Info: Processing ended: Mon Aug 07 20:44:32 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}