hour_counter.hier_info

《Verilog HDL数字控制系统设计实例》-冼进-源代码

|hour_counter
clk => hour_data0[2]~reg0.CLK
clk => hour_data0[1]~reg0.CLK
clk => hour_data0[0]~reg0.CLK
clk => EO~reg0.CLK
clk => hour_data1[3]~reg0.CLK
clk => hour_data1[2]~reg0.CLK
clk => hour_data1[1]~reg0.CLK
clk => hour_data1[0]~reg0.CLK
clk => hour_data0[3]~reg0.CLK
EN => hour_data0~8.OUTPUTSELECT
EN => hour_data0~9.OUTPUTSELECT
EN => hour_data0~10.OUTPUTSELECT
EN => hour_data0~11.OUTPUTSELECT
EN => EO~2.OUTPUTSELECT
EN => hour_data1~12.OUTPUTSELECT
EN => hour_data1~13.OUTPUTSELECT
EN => hour_data1~14.OUTPUTSELECT
EN => hour_data1~15.OUTPUTSELECT
SW1 => ~NO_FANOUT~
SW2 => ~NO_FANOUT~
hour_data1[0] <= hour_data1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data1[1] <= hour_data1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data1[2] <= hour_data1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data1[3] <= hour_data1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data0[0] <= hour_data0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data0[1] <= hour_data0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data0[2] <= hour_data0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_data0[3] <= hour_data0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
EO <= EO~reg0.DB_MAX_OUTPUT_PORT_TYPE