bypass_adder.map.qmsg

为了给大家紧张的工作减轻点负担

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 21 10:26:00 1999 " "Info: Processing started: Thu Jan 21 10:26:00 1999" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bypass_adder -c bypass_adder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bypass_adder -c bypass_adder" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bypass_adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bypass_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bypass_adder-adderbehav " "Info: Found design unit 1: bypass_adder-adderbehav" {  } { { "bypass_adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/wzztemp/adders/bypass_adder/bypass_adder.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bypass_adder " "Info: Found entity 1: bypass_adder" {  } { { "bypass_adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/wzztemp/adders/bypass_adder/bypass_adder.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fa.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fa.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Fa-Fabehav " "Info: Found design unit 1: Fa-Fabehav" {  } { { "fa.vhd" "" { Text "C:/Documents and Settings/new/桌面/wzztemp/adders/bypass_adder/fa.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Fa " "Info: Found entity 1: Fa" {  } { { "fa.vhd" "" { Text "C:/Documents and Settings/new/桌面/wzztemp/adders/bypass_adder/fa.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pgnet.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pgnet.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PGNet-PGbehav " "Info: Found design unit 1: PGNet-PGbehav" {  } { { "pgnet.vhd" "" { Text "C:/Documents and Settings/new/桌面/wzztemp/adders/bypass_adder/pgnet.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PGNet " "Info: Found entity 1: PGNet" {  } { { "pgnet.vhd" "" { Text "C:/Documents and Settings/new/桌面/wzztemp/adders/bypass_adder/pgnet.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "bypass_adder " "Info: Elaborating entity \"bypass_adder\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_COMPARING_UNEQUAL_ARRAYS" "FALSE bypass_adder.vhd(38) " "Warning (10620): VHDL warning at bypass_adder.vhd(38): comparison between unequal length operands always returns FALSE" {  } { { "bypass_adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/wzztemp/adders/bypass_adder/bypass_adder.vhd" 38 0 0 } }  } 0 10620 "VHDL warning at %2!s!: comparison between unequal length operands always returns %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PGNet PGNet:\\G1:0:l1 " "Info: Elaborating entity \"PGNet\" for hierarchy \"PGNet:\\G1:0:l1\"" {  } { { "bypass_adder.vhd" "\\G1:0:l1" { Text "C:/Documents and Settings/new/桌面/wzztemp/adders/bypass_adder/bypass_adder.vhd" 31 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Fa Fa:\\G2:0:l2 " "Info: Elaborating entity \"Fa\" for hierarchy \"Fa:\\G2:0:l2\"" {  } { { "bypass_adder.vhd" "\\G2:0:l2" { Text "C:/Documents and Settings/new/桌面/wzztemp/adders/bypass_adder/bypass_adder.vhd" 35 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "196 " "Info: Implemented 196 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "57 " "Info: Implemented 57 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "57 " "Info: Implemented 57 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "82 " "Info: Implemented 82 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 21 10:26:03 1999 " "Info: Processing ended: Thu Jan 21 10:26:03 1999" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}