fulladd.vhd

来自「为了给大家紧张的工作减轻点负担」· VHDL 代码 · 共 22 行

--一位全加器设计
library ieee;
use ieee.std_logic_1164.all;

entity fulladd is
	port (	A: in std_logic;
		B: in std_logic;
		 cin:in std_logic;
		 sumbit:out std_logic;
		cout:out std_logic
		);
end fulladd;

architecture behav of fulladd is
begin
	sumbit<=(A xor B) xor cin;
	cout<=(a and b) or (cin and a) or (cin and b);
end behav;