bypass_adder.tan.rpt

为了给大家紧张的工作减轻点负担

Timing Analyzer report for bypass_adder
Thu Jan 21 10:26:32 1999
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                    ;
+------------------------------+-------+---------------+-------------+------+---------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+---------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 28.819 ns   ; B[1] ; Sum[27] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;         ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+---------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; tpd                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+-----------------+-------+---------+
; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From  ; To      ;
+-----------------------------------------+-----------------------------------------------------+-----------------+-------+---------+
; N/A                                     ; None                                                ; 28.819 ns       ; B[1]  ; Sum[27] ;
; N/A                                     ; None                                                ; 28.811 ns       ; B[1]  ; Sum[26] ;
; N/A                                     ; None                                                ; 28.467 ns       ; B[1]  ; Sum[25] ;
; N/A                                     ; None                                                ; 28.265 ns       ; A[0]  ; Sum[27] ;
; N/A                                     ; None                                                ; 28.257 ns       ; A[0]  ; Sum[26] ;
; N/A                                     ; None                                                ; 28.092 ns       ; B[1]  ; Sum[24] ;
; N/A                                     ; None                                                ; 27.913 ns       ; A[0]  ; Sum[25] ;
; N/A                                     ; None                                                ; 27.911 ns       ; B[0]  ; Sum[27] ;
; N/A                                     ; None                                                ; 27.903 ns       ; B[0]  ; Sum[26] ;
; N/A                                     ; None                                                ; 27.901 ns       ; Ci    ; Sum[27] ;
; N/A                                     ; None                                                ; 27.893 ns       ; Ci    ; Sum[26] ;
; N/A                                     ; None                                                ; 27.730 ns       ; A[1]  ; Sum[27] ;
; N/A                                     ; None                                                ; 27.722 ns       ; A[1]  ; Sum[26] ;
; N/A                                     ; None                                                ; 27.599 ns       ; B[1]  ; Sum[20] ;
; N/A                                     ; None                                                ; 27.559 ns       ; B[0]  ; Sum[25] ;
; N/A                                     ; None                                                ; 27.549 ns       ; Ci    ; Sum[25] ;
; N/A                                     ; None                                                ; 27.538 ns       ; A[0]  ; Sum[24] ;
; N/A                                     ; None                                                ; 27.378 ns       ; A[1]  ; Sum[25] ;
; N/A                                     ; None                                                ; 27.304 ns       ; B[1]  ; Sum[23] ;
; N/A                                     ; None                                                ; 27.184 ns       ; B[0]  ; Sum[24] ;
; N/A                                     ; None                                                ; 27.174 ns       ; Ci    ; Sum[24] ;
; N/A                                     ; None                                                ; 27.045 ns       ; A[0]  ; Sum[20] ;
; N/A                                     ; None                                                ; 27.004 ns       ; B[1]  ; Sum[22] ;
; N/A                                     ; None                                                ; 27.003 ns       ; A[1]  ; Sum[24] ;
; N/A                                     ; None                                                ; 26.750 ns       ; A[0]  ; Sum[23] ;
; N/A                                     ; None                                                ; 26.701 ns       ; A[2]  ; Sum[27] ;
; N/A                                     ; None                                                ; 26.693 ns       ; A[2]  ; Sum[26] ;
; N/A                                     ; None                                                ; 26.691 ns       ; B[0]  ; Sum[20] ;
; N/A                                     ; None                                                ; 26.681 ns       ; Ci    ; Sum[20] ;
; N/A                                     ; None                                                ; 26.625 ns       ; B[1]  ; Sum[21] ;
; N/A                                     ; None                                                ; 26.510 ns       ; A[1]  ; Sum[20] ;
; N/A                                     ; None                                                ; 26.450 ns       ; A[0]  ; Sum[22] ;
; N/A                                     ; None                                                ; 26.442 ns       ; B[2]  ; Sum[27] ;